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Searched refs:SYS_PLL_PFD0_DIV2 (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-imx/imx9/
A Dclock.c157 case SYS_PLL_PFD0_DIV2: in decode_pll()
449 case SYS_PLL_PFD0_DIV2: in update_pll_pfd_mfn()
494 case SYS_PLL_PFD0_DIV2: in get_clk_src_rate()
856 ccm_clk_root_cfg(ENET_CLK_ROOT, SYS_PLL_PFD0_DIV2, eqos_post_div); in set_clk_eqos()
857 ccm_clk_root_cfg(ENET_TIMER2_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5); in set_clk_eqos()
953 ccm_clk_root_cfg(ENET_REF_CLK_ROOT, SYS_PLL_PFD0_DIV2, div); in set_clk_enet()
954 ccm_clk_root_cfg(ENET_TIMER1_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5); in set_clk_enet()
957 ccm_clk_root_cfg(ENET_REF_PHY_CLK_ROOT, SYS_PLL_PFD0_DIV2, 20); in set_clk_enet()
980 freq = decode_pll(SYS_PLL_PFD0_DIV2); in do_showclocks()
A Dclock_root.c23 { OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, SYS_PLL_PFD2_DIV2 }, /* non-IO */
24 { OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, VIDEO_PLL_CLK }, /* IO*/
/arch/arm/include/asm/arch-imx9/
A Dclock.h28 SYS_PLL_PFD0_DIV2, enumerator

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