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Searched refs:TEGRA_CLK_PLLS (Results 1 – 2 of 2) sorted by relevance

/arch/arm/include/asm/arch-tegra/
A Dclk_rst.h43 TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */ enumerator
77 struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */
/arch/arm/mach-tegra/
A Dclock.c86 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) { in get_pll()
130 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) in clock_start_pll()
575 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) in clock_get_rate()
634 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) in clock_set_rate()

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