1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2016 - 2022, Xilinx, Inc. 4 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. 5 */ 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/bitops.h> 9 #endif 10 11 struct crlapb_regs { 12 u32 reserved0[67]; 13 u32 cpu_r5_ctrl; 14 u32 reserved; 15 u32 iou_switch_ctrl; /* 0x114 */ 16 u32 reserved1[13]; 17 u32 timestamp_ref_ctrl; /* 0x14c */ 18 u32 reserved3[108]; 19 u32 rst_cpu_r5; 20 u32 reserved2[17]; 21 u32 rst_timestamp; /* 0x348 */ 22 }; 23 24 struct iou_scntrs_regs { 25 u32 counter_control_register; /* 0x0 */ 26 u32 reserved0[7]; 27 u32 base_frequency_id_register; /* 0x20 */ 28 }; 29 30 struct crp_regs { 31 u32 reserved0[128]; 32 u32 boot_mode_usr; /* 0x200 */ 33 }; 34 35 #define VERSAL2_CRL_APB_BASEADDR 0xEB5E0000 36 #define VERSAL2_CRP_BASEADDR 0xF1260000 37 #define VERSAL2_IOU_SCNTR_SECURE 0xEC920000 38 39 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25) 40 #define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25) 41 #define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 42 #define IOU_SCNTRS_CONTROL_EN 1 43 44 #define crlapb_base ((struct crlapb_regs *)VERSAL2_CRL_APB_BASEADDR) 45 #define crp_base ((struct crp_regs *)VERSAL2_CRP_BASEADDR) 46 #define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL2_IOU_SCNTR_SECURE) 47 48 #define PMC_TAP 0xF11A0000 49 50 #define PMC_TAP_IDCODE (PMC_TAP + 0) 51 #define PMC_TAP_VERSION (PMC_TAP + 0x4) 52 # define PMC_VERSION_MASK GENMASK(7, 0) 53 # define PS_VERSION_MASK GENMASK(15, 8) 54 # define PS_VERSION_MAJOR GENMASK(7, 4) 55 # define PS_VERSION_MINOR GENMASK(3, 0) 56 # define RTL_VERSION_MASK GENMASK(23, 16) 57 # define PLATFORM_MASK GENMASK(27, 24) 58 # define PLATFORM_VERSION_MASK GENMASK(31, 28) 59 #define PMC_TAP_USERCODE (PMC_TAP + 0x8) 60 61 /* Bootmode setting values */ 62 #define BOOT_MODES_MASK 0x0000000F 63 #define QSPI_MODE_24BIT 0x00000001 64 #define QSPI_MODE_32BIT 0x00000002 65 #define SD_MODE 0x00000003 /* sd 0 */ 66 #define SD_MODE1 0x00000005 /* sd 1 */ 67 #define EMMC_MODE 0x00000006 68 #define USB_MODE 0x00000007 69 #define OSPI_MODE 0x00000008 70 #define SELECTMAP_MODE 0x0000000A 71 #define UFS_MODE 0x0000000B 72 #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ 73 #define JTAG_MODE 0x00000000 74 #define BOOT_MODE_USE_ALT 0x100 75 #define BOOT_MODE_ALT_SHIFT 12 76 77 enum versal2_platform { 78 VERSAL2_SILICON = 0, 79 VERSAL2_SPP = 1, 80 VERSAL2_EMU = 2, 81 VERSAL2_QEMU = 3, 82 VERSAL2_SPP_MMD = 5, 83 VERSAL2_EMU_MMD = 6, 84 }; 85 86 #define VERSAL2_SLCR_BASEADDR 0xF1060000 87 #define VERSAL_AXI_MUX_SEL (VERSAL2_SLCR_BASEADDR + 0x504) 88 #define VERSAL_OSPI_LINEAR_MODE BIT(1) 89 90 #define FLASH_RESET_GPIO 0xc 91 #define WPROT_CRP 0xF126001C 92 #define RST_GPIO 0xF1260318 93 #define WPROT_LPD_MIO 0xFF080728 94 #define WPROT_PMC_MIO 0xF1060828 95 #define BOOT_MODE_DIR 0xF1020204 96 #define BOOT_MODE_OUT 0xF1020208 97 #define MIO_PIN_12 0xF1060030 98 #define BANK0_OUTPUT 0xF1020040 99 #define BANK0_TRI 0xF1060200 100 101 #define PMXC_EFUSE_CACHE_BASE_ADDRESS 0xF1250000 102 #define PMXC_SLCR_BASE_ADDRESS 0xF1061000 103 #define PMXC_UFS_CAL_1_OFFSET 0xBE8 104 #define PMXC_SRAM_CSR 0x4C 105 #define PMXC_TX_RX_CFG_RDY 0x54 106