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Searched refs:__raw_writel (Results 1 – 25 of 34) sorted by relevance

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/arch/arm/mach-keystone/
A Dddr3.c40 __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
50 __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
286 __raw_writel(0, base + KS2_CIC_CTRL); in cic_init()
287 __raw_writel(0, base + KS2_CIC_HOST_CTRL); in cic_init()
376 __raw_writel(tmp, KS2_DDR3APLLCTL1); in ddr3_reset_ddrphy()
407 __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); in ddr3_err_reset_workaround()
408 __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); in ddr3_err_reset_workaround()
418 __raw_writel(tmp_a, KS2_PSC_BASE + in ddr3_err_reset_workaround()
428 __raw_writel(tmp_b, KS2_PSC_BASE + in ddr3_err_reset_workaround()
438 __raw_writel(tmp, KS2_RSTCTRL); in ddr3_err_reset_workaround()
[all …]
A Dpsc.c126 __raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); in psc_set_state()
133 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_state()
138 __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD); in psc_set_state()
182 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_disable_module()
206 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_reset_iso()
227 __raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); in psc_disable_domain()
231 __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD); in psc_disable_domain()
259 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_module_keep_in_reset_enabled()
269 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_module_keep_in_reset_enabled()
273 __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD); in psc_module_keep_in_reset_enabled()
[all …]
A Dinit.c32 __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); in chip_configuration_unlock()
33 __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); in chip_configuration_unlock()
98 __raw_writel(val, KS2_DEVCFG); in config_pcie_mode()
/arch/arm/mach-imx/
A Dtimer.c71 __raw_writel(GPTCR_SWR, &cur_gpt->control); in timer_init()
75 __raw_writel(0, &cur_gpt->control); in timer_init()
93 __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT), in timer_init()
100 __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ in timer_init()
103 __raw_writel(i, &cur_gpt->control); in timer_init()
A Diomux-v3.c62 __raw_writel(mux_mode, base + mux_ctrl_ofs); in imx_iomux_v3_setup_pad()
65 __raw_writel(sel_input, base + sel_input_ofs); in imx_iomux_v3_setup_pad()
69 __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl, in imx_iomux_v3_setup_pad()
73 __raw_writel(pad_ctrl, base + pad_ctrl_ofs); in imx_iomux_v3_setup_pad()
/arch/arm/cpu/armv7/vf610/
A Dtimer.c39 __raw_writel(0, &cur_pit->mcr); in timer_init()
41 __raw_writel(TIMER_LOAD_VAL, &cur_pit->ldval1); in timer_init()
42 __raw_writel(0, &cur_pit->tctrl1); in timer_init()
43 __raw_writel(1, &cur_pit->tctrl1); in timer_init()
/arch/arm/mach-imx/imx8ulp/
A Diomux.c34 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & in imx8ulp_iomux_setup_pad()
38 __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT), base + sel_input_ofs); in imx8ulp_iomux_setup_pad()
41 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & in imx8ulp_iomux_setup_pad()
A Dsoc.c323 __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ in disable_wdog()
324 __raw_writel(REFRESH_WORD1, (wdog_base + 0x04)); in disable_wdog()
329 __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04)); in disable_wdog()
330 __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04)); in disable_wdog()
/arch/powerpc/cpu/mpc83xx/
A Dcpu_init.c156 __raw_writel(~(RSR_RES), &im->reset.rsr); in cpu_init_f()
166 __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr); in cpu_init_f()
182 __raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH, in cpu_init_f()
185 __raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh); in cpu_init_f()
189 __raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl); in cpu_init_f()
192 __raw_writel(CFG_SYS_GPR1, &im->sysconf.gpr1); in cpu_init_f()
195 __raw_writel(CFG_SYS_DDRCDR, &im->sysconf.ddrcdr); in cpu_init_f()
198 __raw_writel(CFG_SYS_OBIR, &im->sysconf.obir); in cpu_init_f()
/arch/arm/mach-imx/mx7ulp/
A Diomux.c44 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & in mx7ulp_iomux_setup_pad()
48 __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT), in mx7ulp_iomux_setup_pad()
52 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & in mx7ulp_iomux_setup_pad()
A Dsoc.c128 __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ in disable_wdog()
129 __raw_writel(REFRESH_WORD1, (wdog_base + 0x04)); in disable_wdog()
134 __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04)); in disable_wdog()
135 __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04)); in disable_wdog()
141 __raw_writel(0x0, wdog_base + 0x0C); /* Set WIN to 0 */ in disable_wdog()
142 __raw_writel(0x400, wdog_base + 0x08); /* Set timeout to default 0x400 */ in disable_wdog()
143 __raw_writel(0x120, wdog_base + 0x00); /* Disable it and set update */ in disable_wdog()
/arch/mips/mach-mscc/include/mach/
A Dddr.h638 __raw_writel(~i, (void __iomem *)(MSCC_DDR_TO + (i * 4))); in dram_check()
727 __raw_writel(~i, (void __iomem *)(MSCC_DDR_TO + (i * 4))); in dram_check()
837 __raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO)); in hal_vcoreiii_wait_memctl()
838 __raw_writel(0x22221111, ((void __iomem *)MSCC_DDR_TO + 0x4)); in hal_vcoreiii_wait_memctl()
839 __raw_writel(0x44443333, ((void __iomem *)MSCC_DDR_TO + 0x8)); in hal_vcoreiii_wait_memctl()
840 __raw_writel(0x66665555, ((void __iomem *)MSCC_DDR_TO + 0xC)); in hal_vcoreiii_wait_memctl()
841 __raw_writel(0x88887777, ((void __iomem *)MSCC_DDR_TO + 0x10)); in hal_vcoreiii_wait_memctl()
842 __raw_writel(0xaaaa9999, ((void __iomem *)MSCC_DDR_TO + 0x14)); in hal_vcoreiii_wait_memctl()
843 __raw_writel(0xccccbbbb, ((void __iomem *)MSCC_DDR_TO + 0x18)); in hal_vcoreiii_wait_memctl()
844 __raw_writel(0xeeeedddd, ((void __iomem *)MSCC_DDR_TO + 0x1C)); in hal_vcoreiii_wait_memctl()
[all …]
/arch/arm/include/asm/arch-mx6/
A Dsys_proto.h36 __raw_writel(io_vol, IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII); in iomuxc_set_rgmii_io_voltage()
/arch/arm/mach-keystone/include/mach/
A Dmux-k2g.h38 __raw_writel(\
A Dclock_defs.h58 #define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
/arch/arm/mach-imx/mx7/
A Dclock_slice.c427 __raw_writel(reg, &imx_ccm->root[clock_id].target_root); in clock_set_src()
483 __raw_writel(reg, &imx_ccm->root[clock_id].target_root); in clock_set_prediv()
542 __raw_writel(reg, &imx_ccm->root[clock_id].target_root); in clock_set_postdiv()
604 __raw_writel(val, &imx_ccm->root[clock_id].target_root); in clock_set_autopostdiv()
664 __raw_writel(val, &imx_ccm->root[clock_id].target_root); in clock_set_target_val()
718 __raw_writel(val, &imx_ccm->root[clock_id].target_root); in clock_root_cfg()
748 __raw_writel(CCM_CLK_ON_MSK, in clock_enable()
751 __raw_writel(CCM_CLK_ON_MSK, in clock_enable()
/arch/sh/include/asm/
A Dio.h51 #define __raw_writel(v, a) __arch_putl(v, a) macro
86 #define outl(v, p) __raw_writel(cpu_to_le32(v), p)
154 #define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
187 #define writel(v, addr) __raw_writel(v, addr)
/arch/arm/include/asm/
A Dio.h75 #define __raw_writel(val, addr) \ macro
115 #define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v)) macro
140 __raw_writel(*buf++, addr); in __raw_writesl()
201 #define writel_relaxed(v, c) __raw_writel((__force u32)cpu_to_le32(v), (c))
245 #define out_32(a,v) __raw_writel(v,a)
330 #define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p))
/arch/powerpc/include/asm/
A Dio.h166 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) in __raw_writel() function
170 #define __raw_writel __raw_writel macro
312 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
/arch/arm/mach-zynq/
A Dps7_spl_init.c42 __raw_writel(val, addr); in iowrite()
/arch/arm/mach-imx/mx6/
A Dclock.c38 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
92 __raw_writel(reg, &imx_ccm->CCGR6); in enable_usboh3_clk()
173 __raw_writel(reg, &imx_ccm->CCGR2); in enable_i2c_clk()
189 __raw_writel(reg, addr); in enable_i2c_clk()
210 __raw_writel(reg, &imx_ccm->CCGR1); in enable_spi_clk()
1229 __raw_writel(reg, &imx_ccm->CCGR0); in hab_caam_clock_enable()
1241 __raw_writel(reg, &imx_ccm->CCGR0); in hab_caam_clock_enable()
1250 __raw_writel(reg, &imx_ccm->CCGR6); in hab_caam_clock_enable()
1294 __raw_writel(reg, &imx_ccm->CCGR6); in enable_eim_clk()
/arch/arm/include/asm/arch-am33xx/
A Dmux_am43xx.h14 __raw_writel(value, (CTRL_BASE + offset));
A Dmux_am33xx.h22 __raw_writel(value, (CTRL_BASE + offset));
/arch/riscv/include/asm/
A Dio.h30 #define __raw_writel(v, a) __arch_putl(v, a) macro
207 #define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
351 #define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
/arch/mips/include/asm/
A Dio.h345 #define __raw_writel __raw_writel in BUILDIO_MEM() macro
401 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr)) in BUILDIO_MEM()

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