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/arch/riscv/include/asm/
A Dcpufeature.h15 .name = #_name, \
16 .property = #_name, \
23 #define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, NULL) argument
24 #define __RISCV_ISA_EXT_DATA_VALIDATE(_name, _id, _validate) \ argument
25 _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, _validate)
28 #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ argument
29 _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \
33 #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ argument
34 _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), NULL)
35 #define __RISCV_ISA_EXT_SUPERSET_VALIDATE(_name, _id, _sub_exts, _validate) \ argument
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/arch/arm/mach-socfpga/include/mach/
A Dreset_manager.h40 #define SOCFPGA_RESET(_name) RSTMGR_##_name argument
/arch/arm/include/asm/
A Dsecure.h22 #define DECLARE_SECURE_SVC(_name, _id, _fn) \ argument
23 static const secure_svc_tbl_t __secure_svc_ ## _name \
/arch/sandbox/include/asm/
A Dstate.h189 #define SANDBOX_STATE_IO(_name, _compat, _read, _write) \ argument
190 ll_entry_declare(struct sandbox_state_io, _name, state_io) = { \
191 .name = __stringify(_name), \
/arch/arm/mach-tegra/tegra124/
A Dxusb-padctl.c86 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ argument
88 .name = _name, \
/arch/arm/mach-tegra/tegra210/
A Dxusb-padctl.c66 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ argument
68 .name = _name, \

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