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/arch/riscv/lib/
A Dmemcpy.S14 mv t6, a0
22 add t0, a0, a2
40 beq a0, a2, 2f
44 sb a5, 0(a0)
45 addi a0, a0, 1
46 bne a0, a2, 1b
94 addi a0, a0, 16*SZREG
106 addi a0, a0, SZREG
120 addi a0, a0, 1
124 mv a0, t6
[all …]
A Dmemmove.S19 sub t0, a0, a1
30 mv t0, a0
31 add a0, a0, a2
49 beq a0, a2, 2f
53 addi a0, a0, -1
54 sb a5, 0(a0)
72 addi a0, a0, -SZREG
86 addi a0, a0, -1
87 sb a5, 0(a0)
91 mv a0, t0
[all …]
A Dstrncmp_zbb.S26 or t2, a0, a1
29 add t4, a0, a2
38 bge a0, t6, 3f
39 REG_L t0, 0(a0)
45 addi a0, a0, SZREG
60 neg a0, a0
61 ori a0, a0, 1
72 li a0, 0
79 lbu t0, 0(a0)
81 addi a0, a0, 1
[all …]
A Dstrcmp_zbb.S25 or t2, a0, a1
33 REG_L t0, 0(a0)
37 addi a0, a0, SZREG
51 sltu a0, t0, t1
52 neg a0, a0
53 ori a0, a0, 1
64 li a0, 0
70 lbu t0, 0(a0)
72 addi a0, a0, 1
78 sub a0, t0, t1
A Dsetjmp.S10 #define STORE_IDX(reg, idx) sd reg, (idx*8)(a0)
11 #define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0)
13 #define STORE_IDX(reg, idx) sw reg, (idx*4)(a0)
14 #define LOAD_IDX(reg, idx) lw reg, (idx*4)(a0)
34 li a0, 0
57 seqz a0, a1
58 add a0, a0, a1
69 li a0, 0
A Dstrlen_zbb.S33 andi t2, a0, SZREG-1
36 andi t0, a0, -SZREG
68 srli a0, t1, 3
69 bgtu t3, a0, 2f
94 add a0, a0, t2
97 add a0, a0, t1
A Dcrt0_riscv_efi.S185 SAVE_LONG(a0, 0)
189 lla a0, ImageBase
192 bne a0, zero, 0f
195 LOAD_LONG(a0, 0)
/arch/mips/mach-octeon/
A Dlowlevel_init.S24 dmfc0 a0, COP0_CVMMEMCTL_REG
25 dins a0, zero, 0, 9
36 dmtc0 a0, COP0_CVMMEMCTL_REG
39 dmfc0 a0, COP0_CVMCTL_REG
41 dmtc0 a0, COP0_CVMCTL_REG
70 ld a0, 0(t0)
74 sd a0, 0(t1)
113 dmfc0 a0, COP0_CVMMEMCTL_REG
114 dins a0, zero, 0, 9
116 dmtc0 a0, COP0_CVMMEMCTL_REG
[all …]
/arch/mips/mach-mtmips/mt7628/
A Dlowlevel_init.S69 li a0, 0
74 1: cache INDEX_STORE_TAG_I, 0(a0)
75 addiu a0, CONFIG_SYS_ICACHE_LINE_SIZE
76 bne a0, a1, 1b
80 li a0, 0
85 2: cache INDEX_STORE_TAG_D, 0(a0)
86 addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE
87 bne a0, a1, 2b
104 and t0, a0, a2
108 cache INDEX_STORE_TAG_D, 0(a0)
[all …]
/arch/xtensa/cpu/
A Dstart.S82 movi a0, 0
227 movi a0, 0
296 callx0 a0
303 ssl a0
304 movi a0, 1
305 sll a0, a0
361 callx0 a0
455 addx4 a0, a2, a0
456 l32i a0, a0, 0
459 callx0 a0
[all …]
/arch/mips/mach-ath79/qca956x/
A Dqca956x-ddr-tap.S18 li a0, 0xbd001f00
20 sw zero, 0x4(a0) /* Place where the number of passing taps are saved. */
21 sw zero, 0x14(a0) /* Place where the last pass tap value is stored */
23 sw a1, 0x10(a0) /* Place where the First pass tap value is stored */
26 li a0, CKSEG1ADDR(AR71XX_RESET_BASE) /* RESET_BASE_ADDRESS */
27 lw a1, 0x1c(a0) /* Reading the RST_RESET_ADDRESS */
30 sw a1, 0x1c(a0)
35 sw a1, 0x1c(a0) /* Taking the RTC out of RESET */
38 li a0, CKSEG1ADDR(QCA956X_RTC_BASE) /* RTC_BASE_ADDRESS */
40 sw a1, 0x0040(a0) /* RTC_SYNC_RESET_ADDRESS */
[all …]
/arch/riscv/cpu/
A Dstart.S50 mv tp, a0
140 mv s0, a0
170 mv a0, s0
237 mv s0, a0
258 beqz a0, 1f
259 mv a1, a0
269 mv a0, zero
382 add a0, t0, t6
393 beqz a0, 1f
394 mv a1, a0
[all …]
/arch/mips/mach-mtmips/mt7621/spl/
A Dlaunch_ll.S35 sll t1, a0
53 bne t2, a0, _next_coherent_core
66 li a0, KSEG0ADDR(CPULAUNCH)
68 addu a0, t1
72 sw t0, LAUNCH_FLAGS(a0)
93 move t0, a0
125 lw a0, LAUNCH_A0(t0)
159 addu t1, t0, a0
196 li a0, 2
214 beqz a0, _vpe1_init_done
[all …]
A Dstart.S168 la a0, __text_start
169 move a1, a0
173 ins a0, a3, 29, 3 # convert to KSEG1
192 la a0, __bss_start
194 1: sw zero, 0(a0)
195 addiu a0, 4
196 ble a0, a1, 1b
222 move a0, zero # a0 <-- boot_flags = 0
/arch/arm/mach-tegra/
A Dpmc.c59 if (res.a0) in tegra_pmc_readl()
60 printf("%s(): SMC failed: %lu\n", __func__, res.a0); in tegra_pmc_readl()
77 if (res.a0) in tegra_pmc_writel()
78 printf("%s(): SMC failed: %lu\n", __func__, res.a0); in tegra_pmc_writel()
/arch/m68k/cpu/mcf5445x/
A Dstart.S20 moveml %d0-%d7/%a0-%a6,%sp@;
203 move.l #0xFC05C000, %a0
206 move.l #0xFC05C00C, %a0
274 jmp (%a0)
310 jmp (%a0)
393 move.l %d0, (%a0)
422 jmp (%a0)
527 move.l %a0, %a3
556 move.l %a0, %a3
560 add.l %a0, %d4
[all …]
/arch/m68k/cpu/mcf532x/
A Dstart.S20 moveml %d0-%d7/%a0-%a6,%sp@;
23 moveml %sp@,%d0-%d7/%a0-%a6; \
116 move.l #(0xFC0a0010), %a0
117 move.w (%a0), %d0
120 move.w %d0, (%a0)
183 move.l 16(%a6), %a0 /* Save copy of Destination Address */
187 move.l %a0, %a3
216 move.l %a0, %a3
220 add.l %a0, %d4
232 move.l %a0, %a1
[all …]
/arch/mips/lib/
A Dgenex.S137 mfc0 a0, CP0_STATUS
138 ori a0, STATMASK
139 xori a0, STATMASK
140 mtc0 a0, CP0_STATUS
142 and a0, v1
146 or v0, a0
190 move a0, sp
211 move a0, sp
A Dcache_init.S93 li a0, \mode
268 PTR_LI a0, CKSEG1ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
269 PTR_ADDU a1, a0, v0
270 2: PTR_ADDIU a0, 64
271 f_fill64 a0, -64, zero
272 bne a0, a1, 2b
430 ins t0, a0, 0, 3
432 xor a0, a0, t0
433 andi a0, a0, CONF_CM_CMASK
434 xor t0, a0, t0
/arch/m68k/cpu/mcf52x2/
A Dstart.S18 moveml %d0-%d7/%a0-%a6,%sp@; \
21 moveml %sp@,%d0-%d7/%a0-%a6; \
138 move.l #(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0
142 move.l (%a0)+, (%a2)+
143 cmp.l %a0, %a1
247 move.l 16(%a6), %a0 /* Save copy of Destination Address */
251 move.l %a0, %a3
279 move.l %a0, %a3
283 add.l %a0, %d4
295 move.l %a0, %a1
[all …]
/arch/arm/mach-owl/
A Dsoc.c66 PSCI_VERSION_MAJOR(res.a0), in show_psci_version()
67 PSCI_VERSION_MINOR(res.a0)); in show_psci_version()
/arch/m68k/cpu/mcf523x/
A Dstart.S17 moveml %d0-%d7/%a0-%a6,%sp@;
20 moveml %sp@,%d0-%d7/%a0-%a6; \
168 move.l 16(%a6), %a0 /* Save copy of Destination Address */
172 move.l %a0, %a3
201 move.l %a0, %a3
205 add.l %a0, %d4
217 move.l %a0, %a1
243 move.l %a0,-(%sp) /* dest_addr */
/arch/m68k/cpu/mcf530x/
A Dstart.S18 moveml %d0-%d7/%a0-%a6,%sp@
22 moveml %sp@,%d0-%d7/%a0-%a6;
172 move.l 16(%a6), %a0 /* Save copy of Destination Address */
176 move.l %a0, %a3
204 move.l %a0, %a3
208 add.l %a0, %d4
220 move.l %a0, %a1
246 move.l %a0,-(%sp) /* dest_addr */
/arch/mips/cpu/
A Dstart.S35 move k1, a0 # preserve a0 in k1
37 li a0, 0 # Use hard register context
274 move a0, zero # a0 <-- boot_flags = 0
/arch/arm/mach-stm32mp/include/mach/
A Dstm32mp1_smc.h49 if (res.a0) { in stm32_smc()
51 __func__, svc, op, res.a0); in stm32_smc()

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