Searched refs:adjust (Results 1 – 16 of 16) sorted by relevance
| /arch/mips/mach-octeon/ |
| A D | cpu.c | 182 int adjust = (1 << 20); in octeon_configure_load_memory() local
185 adjust = (17 << 20); in octeon_configure_load_memory()
190 mem_top = min_t(u64, gd->ram_size - adjust, in octeon_configure_load_memory()
191 (256 << 20) - adjust); in octeon_configure_load_memory()
194 mem_top = min_t(u64, gd->ram_size - adjust, in octeon_configure_load_memory()
195 (512 << 20) - adjust); in octeon_configure_load_memory()
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| /arch/x86/include/asm/acpi/cros_ec/ |
| A D | als.asl | 53 Package () { 70, 30 }, // Min { -30% adjust at 30 lux }
54 Package () { 150, 1000 } // Max { +50% adjust at 1000 lux }
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| /arch/arm/include/asm/arch-octeontx2/csrs/ |
| A D | csrs-nix.h | 3670 u64 adjust : 9; member
6493 u64 adjust : 9; member
6511 u64 adjust : 9; member
6529 u64 adjust : 9; member
6565 u64 adjust : 9; member
6583 u64 adjust : 9; member
6601 u64 adjust : 9; member
6756 u64 adjust : 9; member
6762 u64 adjust : 9; member
7055 u64 adjust : 9; member
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| /arch/arm/dts/ |
| A D | socfpga_arria5_socdk.dts | 92 * adjust the falling times to decrease the i2c frequency to 50Khz
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| A D | socfpga_cyclone5_socdk.dts | 96 * adjust the falling times to decrease the i2c frequency to 50Khz
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| A D | socfpga_arria10_socdk.dtsi | 131 * adjust the falling times to decrease the i2c frequency to 50Khz
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| A D | imx93-11x11-frdm.dts | 324 samsung,picophy-dc-vol-level-adjust = <7>;
339 samsung,picophy-dc-vol-level-adjust = <7>;
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| A D | imx91-11x11-evk.dts | 415 samsung,picophy-dc-vol-level-adjust = <7>;
433 samsung,picophy-dc-vol-level-adjust = <7>;
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| A D | armada-xp-synology-ds414.dts | 17 * installing it from u-boot prompt) or adjust the Devive Tree
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| A D | imx8mn-evk.dtsi | 266 samsung,picophy-dc-vol-level-adjust = <7>;
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| A D | rk3288-veyron.dtsi | 522 /* We need to go faster than 24MHz, so adjust clock parents / rates */
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| A D | rk3368.dtsi | 778 temp_adjust: temp-adjust@1f {
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| /arch/arm/mach-k3/r5/ |
| A D | Kconfig | 9 MPU core voltage and adjust frequency according to SoC TRM
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| /arch/mips/mach-mscc/include/mach/ |
| A D | ddr.h | 357 static inline bool adjust_dly(int adjust) in adjust_dly() argument
362 writel(r + adjust, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(0)); in adjust_dly()
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| /arch/mips/mach-octeon/include/mach/ |
| A D | cvmx-pko-defs.h | 577 u64 adjust : 9; member
701 u64 adjust : 9; member
711 u64 adjust : 9; member
1174 u64 adjust : 9; member
1281 u64 adjust : 9; member
1289 u64 adjust : 9; member
1562 u64 adjust : 9; member
1696 u64 adjust : 9; member
1706 u64 adjust : 9; member
1963 u64 adjust : 9; member
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| /arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| A D | README.lsch3 | 168 to adjust accordingly.
218 need to adjust accordingly for SD/eMMC
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