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Searched refs:apll_mdiv (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init.h23 unsigned apll_mdiv; member
44 unsigned apll_mdiv; member
A Dclock_init_exynos5.c27 .apll_mdiv = 0x96,
44 .apll_mdiv = 0xc8,
59 .apll_mdiv = 0x64,
74 .apll_mdiv = 0x7d,
89 .apll_mdiv = 0x96,
104 .apll_mdiv = 0xaf,
119 .apll_mdiv = 0x1a9,
618 val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, in exynos5250_system_clock_init()
819 val = set_pll(arm_clk_ratio->apll_mdiv, in exynos5420_system_clock_init()

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