Searched refs:assign (Results 1 – 9 of 9) sorted by relevance
| /arch/powerpc/cpu/mpc83xx/ |
| A D | qe_io.c | 29 int open_drain, int assign) in qe_cfg_iopin() argument
71 dbit_asgn = (u32)(assign << offset); in qe_cfg_iopin()
96 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) in qe_config_iopin() argument
101 qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign); in qe_config_iopin()
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| A D | cpu_init.c | 35 int open_drain, int assign);
41 int dir, open_drain, assign; in config_qe_ioports() local
44 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { in config_qe_ioports()
49 assign = qe_iop_conf_tab[i].assign; in config_qe_ioports()
50 qe_config_iopin(port, pin, dir, open_drain, assign); in config_qe_ioports()
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| /arch/powerpc/cpu/mpc85xx/ |
| A D | qe_io.c | 16 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) in qe_config_iopin() argument
58 pin_2bit_assign = (u32)(assign in qe_config_iopin()
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| A D | cpu_init.c | 134 int open_drain, int assign);
141 int dir, open_drain, assign; in config_qe_ioports() local
144 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { in config_qe_ioports()
149 assign = qe_iop_conf_tab[i].assign; in config_qe_ioports()
150 qe_config_iopin(port, pin, dir, open_drain, assign); in config_qe_ioports()
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| /arch/arm/dts/ |
| A D | imx6ul-kontron-bl-common-u-boot.dtsi | 30 * in Linux we can't assign the shared reset GPIO to the PHYs, as this
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| A D | armada-388-clearfog.dts | 278 * PCIe uses ARP to assign addresses, or
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| /arch/x86/dts/ |
| A D | baytrail_som-db5800-som-6867.dts | 48 pull-assign = <1>;
61 pull-assign = <1>;
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| A D | chromebook_coral.dts | 811 * If the Board has PERST_0 signal, assign the GPIO
812 * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
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| /arch/arm/mach-imx/ |
| A D | Kconfig | 30 i.MX Resource domain controller is used to assign masters
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