1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010,2011
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 #include <config.h>
8 #include <dm.h>
9 #include <dm/root.h>
10 #include <env.h>
11 #include <errno.h>
12 #include <init.h>
13 #include <log.h>
14 #include <ns16550.h>
15 #include <power/regulator.h>
16 #include <usb.h>
17 #include <asm/global_data.h>
18 #include <asm/io.h>
19 #include <asm/arch-tegra/ap.h>
20 #include <asm/arch-tegra/board.h>
21 #include <asm/arch-tegra/cboot.h>
22 #include <asm/arch-tegra/clk_rst.h>
23 #include <asm/arch-tegra/pmc.h>
24 #include <asm/arch-tegra/pmu.h>
25 #include <asm/arch-tegra/sys_proto.h>
26 #include <asm/arch-tegra/uart.h>
27 #include <asm/arch-tegra/warmboot.h>
28 #include <asm/arch-tegra/gpu.h>
29 #include <asm/arch-tegra/usb.h>
30 #include <asm/arch-tegra/xusb-padctl.h>
31 #ifndef CONFIG_TEGRA186
32 #include <asm/arch-tegra/fuse.h>
33 #include <asm/arch/gp_padctrl.h>
34 #endif
35 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
36 #include <asm/arch/clock.h>
37 #endif
38 #if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
39 #include <asm/arch/funcmux.h>
40 #include <asm/arch/pinmux.h>
41 #endif
42 #include <asm/arch/tegra.h>
43 #ifdef CONFIG_TEGRA_CLOCK_SCALING
44 #include <asm/arch/emc.h>
45 #endif
46 #include "emc.h"
47
48 DECLARE_GLOBAL_DATA_PTR;
49
50 #ifdef CONFIG_XPL_BUILD
51 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
52 U_BOOT_DRVINFO(tegra_gpios) = {
53 "gpio_tegra"
54 };
55 #endif
56
pinmux_init(void)57 __weak void pinmux_init(void) {}
pin_mux_usb(void)58 __weak void pin_mux_usb(void) {}
pin_mux_spi(void)59 __weak void pin_mux_spi(void) {}
pin_mux_mmc(void)60 __weak void pin_mux_mmc(void) {}
gpio_early_init_uart(void)61 __weak void gpio_early_init_uart(void) {}
pin_mux_display(void)62 __weak void pin_mux_display(void) {}
start_cpu_fan(void)63 __weak void start_cpu_fan(void) {}
cboot_late_init(void)64 __weak void cboot_late_init(void) {}
nvidia_board_late_init(void)65 __weak void nvidia_board_late_init(void) {}
66
67 #if defined(CONFIG_TEGRA_NAND)
pin_mux_nand(void)68 __weak void pin_mux_nand(void)
69 {
70 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
71 }
72 #endif
73
74 /*
75 * Routine: power_det_init
76 * Description: turn off power detects
77 */
power_det_init(void)78 static void power_det_init(void)
79 {
80 #if defined(CONFIG_TEGRA20)
81 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
82
83 /* turn off power detects */
84 writel(0, &pmc->pmc_pwr_det_latch);
85 writel(0, &pmc->pmc_pwr_det);
86 #endif
87 }
88
tegra_board_id(void)89 __weak int tegra_board_id(void)
90 {
91 return -1;
92 }
93
94 #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)95 int checkboard(void)
96 {
97 int board_id = tegra_board_id();
98
99 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
100 if (board_id != -1)
101 printf(", ID: %d\n", board_id);
102 printf("\n");
103
104 return 0;
105 }
106 #endif /* CONFIG_DISPLAY_BOARDINFO */
107
tegra_lcd_pmic_init(int board_it)108 __weak int tegra_lcd_pmic_init(int board_it)
109 {
110 return 0;
111 }
112
nvidia_board_init(void)113 __weak int nvidia_board_init(void)
114 {
115 return 0;
116 }
117
118 /*
119 * Routine: board_init
120 * Description: Early hardware init.
121 */
board_init(void)122 int board_init(void)
123 {
124 __maybe_unused int err;
125 __maybe_unused int board_id;
126
127 /* Do clocks and UART first so that printf() works */
128 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
129 clock_init();
130 clock_verify();
131 #endif
132
133 tegra_gpu_config();
134
135 #ifdef CONFIG_TEGRA_SPI
136 pin_mux_spi();
137 #endif
138
139 #ifdef CONFIG_MMC_SDHCI_TEGRA
140 pin_mux_mmc();
141 #endif
142
143 /* Init is handled automatically in the driver-model case */
144 #if defined(CONFIG_VIDEO)
145 pin_mux_display();
146 #endif
147 /* boot param addr */
148 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
149
150 power_det_init();
151
152 #ifdef CONFIG_SYS_I2C_TEGRA
153 # ifdef CONFIG_TEGRA_PMU
154 if (pmu_set_nominal())
155 debug("Failed to select nominal voltages\n");
156 # ifdef CONFIG_TEGRA_CLOCK_SCALING
157 err = board_emc_init();
158 if (err)
159 debug("Memory controller init failed: %d\n", err);
160 # endif
161 # endif /* CONFIG_TEGRA_PMU */
162 #endif /* CONFIG_SYS_I2C_TEGRA */
163
164 #ifdef CONFIG_USB_EHCI_TEGRA
165 pin_mux_usb();
166 #endif
167
168 #if defined(CONFIG_VIDEO)
169 board_id = tegra_board_id();
170 err = tegra_lcd_pmic_init(board_id);
171 if (err) {
172 debug("Failed to set up LCD PMIC\n");
173 return err;
174 }
175 #endif
176
177 #ifdef CONFIG_TEGRA_NAND
178 pin_mux_nand();
179 #endif
180
181 tegra_xusb_padctl_init();
182
183 #ifdef CONFIG_TEGRA_LP0
184 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
185 warmboot_save_sdram_params();
186
187 /* prepare the WB code to LP0 location */
188 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
189 #endif
190
191 return nvidia_board_init();
192 }
193
board_cleanup_before_linux(void)194 void board_cleanup_before_linux(void)
195 {
196 /* power down UPHY PLL */
197 tegra_xusb_padctl_exit();
198 }
199
200 #ifdef CONFIG_BOARD_EARLY_INIT_F
__gpio_early_init(void)201 static void __gpio_early_init(void)
202 {
203 }
204
205 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
206
board_early_init_f(void)207 int board_early_init_f(void)
208 {
209 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
210 if (!clock_early_init_done())
211 clock_early_init();
212 #endif
213
214 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
215 #define USBCMD_FS2 (1 << 15)
216 {
217 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
218 writel(USBCMD_FS2, &usbctlr->usb_cmd);
219 }
220 #endif
221
222 /* Do any special system timer/TSC setup */
223 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
224 # if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
225 if (!tegra_cpu_is_non_secure())
226 # endif
227 arch_timer_init();
228 #endif
229
230 pinmux_init();
231 board_init_uart_f();
232
233 /* Initialize periph GPIOs */
234 gpio_early_init();
235 gpio_early_init_uart();
236
237 return 0;
238 }
239 #endif /* EARLY_INIT */
240
241 #ifndef CONFIG_TEGRA186
nvidia_board_late_init_generic(void)242 static void nvidia_board_late_init_generic(void)
243 {
244 char serialno_str[17];
245
246 /* Set chip id as serialno */
247 sprintf(serialno_str, "%016llx", tegra_chip_uid());
248 env_set("serial#", serialno_str);
249
250 switch (tegra_get_chip()) {
251 case CHIPID_TEGRA20:
252 env_set("platform", "tegra20");
253 break;
254 case CHIPID_TEGRA30:
255 env_set("platform", "tegra30");
256 break;
257 case CHIPID_TEGRA114:
258 env_set("platform", "tegra114");
259 break;
260 case CHIPID_TEGRA124:
261 env_set("platform", "tegra124");
262 break;
263 case CHIPID_TEGRA210:
264 env_set("platform", "tegra210");
265 break;
266 default:
267 return;
268 }
269 }
270 #endif
271
board_late_init(void)272 int board_late_init(void)
273 {
274 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
275 if (tegra_cpu_is_non_secure()) {
276 printf("CPU is in NS mode\n");
277 env_set("cpu_ns_mode", "1");
278 } else {
279 env_set("cpu_ns_mode", "");
280 }
281 #endif
282 start_cpu_fan();
283 cboot_late_init();
284
285 /*
286 * Perform generic env setup in case
287 * vendor does not provide it.
288 */
289 #ifndef CONFIG_TEGRA186
290 nvidia_board_late_init_generic();
291 #endif
292 nvidia_board_late_init();
293
294 return 0;
295 }
296
297 /*
298 * In some SW environments, a memory carve-out exists to house a secure
299 * monitor, a trusted OS, and/or various statically allocated media buffers.
300 *
301 * This carveout exists at the highest possible address that is within a
302 * 32-bit physical address space.
303 *
304 * This function returns the total size of this carve-out. At present, the
305 * returned value is hard-coded for simplicity. In the future, it may be
306 * possible to determine the carve-out size:
307 * - By querying some run-time information source, such as:
308 * - A structure passed to U-Boot by earlier boot software.
309 * - SoC registers.
310 * - A call into the secure monitor.
311 * - In the per-board U-Boot configuration header, based on knowledge of the
312 * SW environment that U-Boot is being built for.
313 *
314 * For now, we support two configurations in U-Boot:
315 * - 32-bit ports without any form of carve-out.
316 * - 64 bit ports which are assumed to use a carve-out of a conservatively
317 * hard-coded size.
318 */
carveout_size(void)319 static ulong carveout_size(void)
320 {
321 #ifdef CONFIG_ARM64
322 return SZ_512M;
323 #elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
324 // BASE+SIZE might not == 4GB. If so, we want the carveout to cover
325 // from BASE to 4GB, not BASE to BASE+SIZE.
326 return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1);
327 #else
328 return 0;
329 #endif
330 }
331
332 /*
333 * Determine the amount of usable RAM below 4GiB, taking into account any
334 * carve-out that may be assigned.
335 */
usable_ram_size_below_4g(void)336 static ulong usable_ram_size_below_4g(void)
337 {
338 ulong total_size_below_4g;
339 ulong usable_size_below_4g;
340
341 /*
342 * The total size of RAM below 4GiB is the lesser address of:
343 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
344 * (b) The size RAM physically present in the system.
345 */
346 if (gd->ram_size < SZ_2G)
347 total_size_below_4g = gd->ram_size;
348 else
349 total_size_below_4g = SZ_2G;
350
351 /* Calculate usable RAM by subtracting out any carve-out size */
352 usable_size_below_4g = total_size_below_4g - carveout_size();
353
354 return usable_size_below_4g;
355 }
356
357 /*
358 * Represent all available RAM in either one or two banks.
359 *
360 * The first bank describes any usable RAM below 4GiB.
361 * The second bank describes any RAM above 4GiB.
362 *
363 * This split is driven by the following requirements:
364 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
365 * property for memory below and above the 4GiB boundary. The layout of that
366 * DT property is directly driven by the entries in the U-Boot bank array.
367 * - The potential existence of a carve-out at the end of RAM below 4GiB can
368 * only be represented using multiple banks.
369 *
370 * Explicitly removing the carve-out RAM from the bank entries makes the RAM
371 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
372 * command-line.
373 *
374 * This does mean that the DT U-Boot passes to the Linux kernel will not
375 * include this RAM in /memory/reg at all. An alternative would be to include
376 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
377 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
378 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
379 * mapping, so either way is acceptable.
380 *
381 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
382 * start address of that bank cannot be represented in the 32-bit .size
383 * field.
384 */
dram_init_banksize(void)385 int dram_init_banksize(void)
386 {
387 int err;
388
389 /* try to compute DRAM bank size based on cboot DTB first */
390 err = cboot_dram_init_banksize();
391 if (err == 0)
392 return err;
393
394 /* fall back to default DRAM bank size computation */
395
396 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
397 gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
398
399 #ifdef CONFIG_PHYS_64BIT
400 if (gd->ram_size > SZ_2G) {
401 gd->bd->bi_dram[1].start = 0x100000000;
402 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
403 } else
404 #endif
405 {
406 gd->bd->bi_dram[1].start = 0;
407 gd->bd->bi_dram[1].size = 0;
408 }
409
410 return 0;
411 }
412
413 /*
414 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
415 * 32-bits of the physical address space. Cap the maximum usable RAM area
416 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
417 * boundary that most devices can address. Also, don't let U-Boot use any
418 * carve-out, as mentioned above.
419 *
420 * This function is called before dram_init_banksize(), so we can't simply
421 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
422 */
board_get_usable_ram_top(phys_size_t total_size)423 phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
424 {
425 ulong ram_top;
426
427 /* try to get top of usable RAM based on cboot DTB first */
428 ram_top = cboot_get_usable_ram_top(total_size);
429 if (ram_top > 0)
430 return ram_top;
431
432 /* fall back to default usable RAM computation */
433
434 return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
435 }
436
437 #if IS_ENABLED(CONFIG_DTB_RESELECT)
embedded_dtb_select(void)438 int embedded_dtb_select(void)
439 {
440 int ret, rescan;
441
442 ret = fdtdec_resetup(&rescan);
443 if (!ret && rescan) {
444 dm_uninit();
445 dm_init_and_scan(true);
446 }
447
448 return 0;
449 }
450 #endif
451