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/arch/x86/lib/
A Dmrccache.c46 return cache && (cache->signature == MRC_DATA_SIGNATURE); in is_mrc_cache()
57 cache = NULL; in mrccache_find_current()
63 cache = next; in mrccache_find_current()
75 if (cache->checksum != compute_ip_checksum(cache->data, in mrccache_find_current()
83 return cache; in mrccache_find_current()
122 return cache; in find_next_mrc_cache()
154 if (cache && (cache->data_size == cur->data_size) && in mrccache_update()
161 if (cache) in mrccache_update()
205 memcpy(cache->data, mrc->buf, cache->data_size); in mrccache_setup()
207 mrc->cache = cache; in mrccache_setup()
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/arch/arm/dts/
A Dsynquacer-sc2a11-caches.dtsi9 i-cache-size = <0x8000>; \
10 i-cache-line-size = <64>; \
11 i-cache-sets = <256>; \
12 d-cache-size = <0x8000>; \
13 d-cache-line-size = <64>; \
41 L3: l3-cache {
42 cache-level = <3>;
43 cache-size = <0x400000>;
44 cache-line-size = <64>;
45 cache-sets = <4096>;
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A Djuno-r2.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
113 i-cache-sets = <256>;
116 d-cache-sets = <256>;
131 i-cache-sets = <256>;
134 d-cache-sets = <128>;
149 i-cache-sets = <256>;
152 d-cache-sets = <128>;
167 i-cache-sets = <256>;
200 cache-sets = <2048>;
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A Dvf610.dtsi8 next-level-cache = <&L2>;
12 L2: cache-controller@40006000 {
13 compatible = "arm,pl310-cache";
15 cache-unified;
16 cache-level = <2>;
A Dnuvoton-npcm845.dtsi20 next-level-cache = <&l2>;
29 next-level-cache = <&l2>;
38 next-level-cache = <&l2>;
47 next-level-cache = <&l2>;
51 l2: l2-cache {
52 compatible = "cache";
A Dfsl-imx8-ca35.dtsi20 next-level-cache = <&A35_L2>;
29 next-level-cache = <&A35_L2>;
38 next-level-cache = <&A35_L2>;
47 next-level-cache = <&A35_L2>;
52 compatible = "cache";
A Dmt8365.dtsi135 i-cache-sets = <256>;
138 d-cache-sets = <256>;
155 i-cache-sets = <256>;
158 d-cache-sets = <256>;
175 i-cache-sets = <256>;
178 d-cache-sets = <256>;
195 i-cache-sets = <256>;
237 l2: l2-cache {
239 cache-level = <2>;
242 cache-sets = <512>;
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A Dhpe-gxp.dtsi21 next-level-cache = <&L2>;
48 L2: cache-controller@b0040000 {
49 compatible = "arm,pl310-cache";
51 cache-unified;
52 cache-level = <2>;
/arch/riscv/dts/
A Dk1.dtsi78 i-cache-sets = <128>;
81 d-cache-sets = <128>;
108 i-cache-sets = <128>;
111 d-cache-sets = <128>;
138 i-cache-sets = <128>;
305 cache-level = <2>;
307 cache-sets = <512>;
308 cache-unified;
314 cache-level = <2>;
316 cache-sets = <512>;
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A Dfu540-c000.dtsi29 i-cache-sets = <128>;
30 i-cache-size = <16384>;
43 d-cache-sets = <64>;
49 i-cache-sets = <64>;
67 d-cache-sets = <64>;
73 i-cache-sets = <64>;
91 d-cache-sets = <64>;
97 i-cache-sets = <64>;
115 d-cache-sets = <64>;
263 cache-level = <2>;
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A Dfu740-c000.dtsi29 i-cache-sets = <128>;
30 i-cache-size = <16384>;
44 d-cache-sets = <64>;
45 d-cache-size = <32768>;
50 i-cache-sets = <128>;
68 d-cache-sets = <64>;
74 i-cache-sets = <128>;
92 d-cache-sets = <64>;
116 d-cache-sets = <64>;
271 cache-level = <2>;
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A Dqilai-voyager.dts39 i-cache-size = <0x8000>;
41 d-cache-size = <0x8000>;
43 next-level-cache = <&L2>;
62 i-cache-size = <0x8000>;
64 d-cache-size = <0x8000>;
85 i-cache-size = <0x8000>;
87 d-cache-size = <0x8000>;
122 L2: l2-cache@200000 {
123 compatible = "cache";
124 cache-level = <0x2>;
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A Dae350_32.dts38 i-cache-size = <0x8000>;
39 i-cache-line-size = <32>;
40 d-cache-size = <0x8000>;
41 d-cache-line-size = <32>;
42 next-level-cache = <&L2>;
59 i-cache-size = <0x8000>;
61 d-cache-size = <0x8000>;
114 L2: l2-cache@e0500000 {
115 compatible = "cache";
116 cache-level = <2>;
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A Dae350_64.dts38 i-cache-size = <0x8000>;
39 i-cache-line-size = <32>;
40 d-cache-size = <0x8000>;
41 d-cache-line-size = <32>;
42 next-level-cache = <&L2>;
59 i-cache-size = <0x8000>;
61 d-cache-size = <0x8000>;
114 L2: l2-cache@e0500000 {
115 compatible = "cache";
116 cache-level = <2>;
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A Dth1520.dtsi28 i-cache-size = <65536>;
29 i-cache-sets = <512>;
31 d-cache-size = <65536>;
32 d-cache-sets = <512>;
51 i-cache-sets = <512>;
54 d-cache-sets = <512>;
73 i-cache-sets = <512>;
109 l2_cache: l2-cache {
112 cache-level = <2>;
114 cache-sets = <1024>;
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/arch/powerpc/dts/
A Dt104xsi-pre.dtsi51 next-level-cache = <&L2_1>;
53 L2_1: l2-cache {
54 next-level-cache = <&cpc>;
61 next-level-cache = <&L2_2>;
63 L2_2: l2-cache {
64 next-level-cache = <&cpc>;
71 next-level-cache = <&L2_3>;
73 L2_3: l2-cache {
74 next-level-cache = <&cpc>;
81 next-level-cache = <&L2_4>;
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/arch/x86/lib/fsp2/
A Dfsp_meminit.c24 struct mrc_data_container *cache; in prepare_mrc_cache_type() local
31 cache = mrccache_find_current(&entry); in prepare_mrc_cache_type()
32 if (!cache) in prepare_mrc_cache_type()
35 log_debug("MRC at %x, size %x\n", (uint)cache->data, cache->data_size); in prepare_mrc_cache_type()
36 *cachep = cache; in prepare_mrc_cache_type()
43 struct mrc_data_container *cache; in prepare_mrc_cache() local
46 ret = prepare_mrc_cache_type(MRC_TYPE_NORMAL, &cache); in prepare_mrc_cache()
49 upd->arch.nvs_buffer_ptr = cache->data; in prepare_mrc_cache()
51 ret = prepare_mrc_cache_type(MRC_TYPE_VAR, &cache); in prepare_mrc_cache()
54 upd->config.variable_nvs_buffer_ptr = cache->data; in prepare_mrc_cache()
/arch/arm/cpu/armv7/
A Dcache_v7_asm.S32 mov r10, #0 @ start clean at cache level 0
35 mov r1, r0, lsr r2 @ extract cache type bits from clidr
37 cmp r1, #2 @ see what cache we have at this level
38 blt skip @ skip if no cache, or just i-cache
64 add r10, r10, #2 @ increment cache number
68 mov r10, #0 @ swith back to cache level 0
102 mov r10, #0 @ start clean at cache level 0
107 cmp r1, #2 @ see what cache we have at this level
108 blt inval_skip @ skip if no cache, or just i-cache
134 add r10, r10, #2 @ increment cache number
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/arch/x86/lib/fsp1/
A Dfsp_common.c26 struct mrc_data_container *cache; in fsp_prepare_mrc_cache() local
34 cache = mrccache_find_current(&entry); in fsp_prepare_mrc_cache()
35 if (!cache) in fsp_prepare_mrc_cache()
39 cache->data, cache->data_size, cache->checksum); in fsp_prepare_mrc_cache()
41 return cache->data; in fsp_prepare_mrc_cache()
/arch/x86/cpu/quark/
A Ddram.c25 struct mrc_data_container *cache; in prepare_mrc_cache() local
33 cache = mrccache_find_current(&entry); in prepare_mrc_cache()
34 if (!cache) in prepare_mrc_cache()
38 cache->data, cache->data_size, cache->checksum); in prepare_mrc_cache()
41 memcpy(&mrc_params->timings, cache->data, cache->data_size); in prepare_mrc_cache()
131 char *cache; in dram_init() local
157 cache = malloc(sizeof(struct mrc_timings)); in dram_init()
158 if (cache) { in dram_init()
161 memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings)); in dram_init()
162 mrc->buf = cache; in dram_init()
/arch/arc/lib/
A Dcpu.c64 const bool cache; member
83 bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD); in arc_em_version() local
89 if (em_versions[i].cache == cache && in arc_em_version()
120 const bool cache; member
142 bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD); in arc_hs_version() local
149 if (hs_versions[i].cache == cache && in arc_hs_version()
/arch/arm/lib/
A Dacpi_table.c136 struct acpi_pptt_cache *cache = ctx->current; in acpi_pptt_add_cache() local
140 cache->hdr.type = ACPI_PPTT_TYPE_CACHE; in acpi_pptt_add_cache()
141 cache->hdr.length = sizeof(struct acpi_pptt_cache); in acpi_pptt_add_cache()
142 cache->flags = flags; in acpi_pptt_add_cache()
143 cache->next_cache_level = next_cache_level; in acpi_pptt_add_cache()
144 cache->size = size; in acpi_pptt_add_cache()
145 cache->sets = sets; in acpi_pptt_add_cache()
146 cache->assoc = assoc; in acpi_pptt_add_cache()
147 cache->attributes = attributes; in acpi_pptt_add_cache()
148 cache->line_size = line_size; in acpi_pptt_add_cache()
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/arch/arm/cpu/armv7m/
A Dcache.c67 static void get_cache_ways_sets(struct dcache_config *cache) in get_cache_ways_sets() argument
71 cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; in get_cache_ways_sets()
72 cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT; in get_cache_ways_sets()
176 struct dcache_config cache; in action_dcache_all() local
188 get_cache_ways_sets(&cache); /* Get number of ways & sets */ in action_dcache_all()
189 debug("cache: ways= %d, sets= %d\n", cache.ways + 1, cache.sets + 1); in action_dcache_all()
190 for (i = cache.sets; i >= 0; i--) { in action_dcache_all()
191 for (j = cache.ways; j >= 0; j--) { in action_dcache_all()
/arch/powerpc/cpu/mpc83xx/bats/
A DKconfig69 bool "I-cache Inhibited"
75 bool "D-cache Write-through"
78 bool "D-cache Inhibited"
84 bool "D-cache Guarded"
214 bool "I-cache Inhibited"
223 bool "D-cache Inhibited"
229 bool "D-cache Guarded"
374 bool "D-cache Guarded"
519 bool "D-cache Guarded"
666 bool "D-cache Guarded"
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/arch/powerpc/cpu/mpc83xx/hid/
A DKconfig9 bool "Enable cache parity errors"
50 bool "Enable instruction cache"
53 bool "Enable data cache"
56 bool "Lock instruction cache"
59 bool "Lock data cache"
90 bool "Enable cache parity errors"
131 bool "Enable instruction cache"
134 bool "Enable data cache"
137 bool "Lock instruction cache"
140 bool "Lock data cache"
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