Searched refs:cache_loop (Results 1 – 3 of 3) sorted by relevance
| /arch/mips/lib/ |
| A D | cache.c | 96 #define cache_loop(start, end, lsize, ops...) do { \ macro
123 cache_loop(start_addr, start_addr + size, ilsize, in flush_cache()
129 cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D); in flush_cache()
132 cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD); in flush_cache()
135 cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); in flush_cache()
154 cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D); in flush_dcache_range()
157 cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); in flush_dcache_range()
173 cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); in invalidate_dcache_range()
175 cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); in invalidate_dcache_range()
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| A D | cache_init.S | 38 .macro cache_loop curr, end, line_sz, op macro
323 cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
327 cache_loop t0, t1, R_IC_LINE, FILL
330 cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
346 cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
355 cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
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| /arch/mips/mach-mtmips/mt7621/spl/ |
| A D | launch_ll.S | 17 .macro cache_loop curr, end, line_sz, op macro
161 cache_loop t0, t1, a1, INDEX_STORE_TAG_I
165 cache_loop t0, t1, a1, FILL
168 cache_loop t0, t1, a1, INDEX_STORE_TAG_I
177 cache_loop t0, t1, a3, INDEX_STORE_TAG_D
186 cache_loop t0, t1, a3, INDEX_STORE_TAG_D
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