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Searched refs:cfg (Results 1 – 25 of 151) sorted by relevance

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/arch/arm/dts/
A Dk3-binman.dtsi33 board-cfg {
40 pm-cfg {
47 rm-cfg {
54 sec-cfg {
148 pm-cfg.bin {
162 rm-cfg.bin {
213 board-cfg {
219 pm-cfg.bin {
224 pm-cfg {
234 rm-cfg {
[all …]
A Dk3-j721e-r5-beagleboneai64.dts69 board-cfg.bin {
70 description = "board-cfg";
78 pm-cfg.bin {
79 description = "pm-cfg";
84 filename = "pm-cfg.bin";
87 rm-cfg.bin {
88 description = "rm-cfg";
93 filename = "rm-cfg.bin";
96 sec-cfg.bin {
97 description = "sec-cfg";
[all …]
A Dk3-j721e-binman.dtsi90 board-cfg.bin {
98 pm-cfg.bin {
106 rm-cfg.bin {
114 sec-cfg.bin {
173 board-cfg {
179 pm-cfg.bin {
184 pm-cfg {
189 rm-cfg.bin {
194 rm-cfg {
199 sec-cfg.bin {
[all …]
A Dk3-j784s4-binman.dtsi11 config = "tifs-rm-cfg.yaml";
44 combined_tifs_cfg: combined-tifs-cfg.bin {
45 filename = "combined-tifs-cfg.bin";
53 combined_dm_cfg: combined-dm-cfg.bin {
54 filename = "combined-dm-cfg.bin";
91 combined_tifs_cfg_fs: combined-tifs-cfg.bin {
92 filename = "combined-tifs-cfg.bin";
100 combined_dm_cfg_fs: combined-dm-cfg.bin {
101 filename = "combined-dm-cfg.bin";
137 filename = "combined-tifs-cfg.bin";
[all …]
A Dk3-j7200-binman.dtsi40 filename = "combined-tifs-cfg.bin";
48 filename = "combined-dm-cfg.bin";
83 filename = "combined-tifs-cfg.bin";
90 combined_dm_cfg: combined-dm-cfg.bin {
91 filename = "combined-dm-cfg.bin";
128 filename = "combined-tifs-cfg.bin";
136 filename = "combined-dm-cfg.bin";
171 filename = "combined-tifs-cfg.bin";
179 filename = "combined-dm-cfg.bin";
213 filename = "combined-tifs-cfg.bin";
[all …]
A Dk3-j722s-binman.dtsi41 combined_tifs_cfg: combined-tifs-cfg.bin {
42 filename = "combined-tifs-cfg.bin";
51 combined_dm_cfg: combined-dm-cfg.bin {
52 filename = "combined-dm-cfg.bin";
91 combined_tifs_cfg_fs: combined-tifs-cfg.bin {
92 filename = "combined-tifs-cfg.bin";
101 combined_dm_cfg_fs: combined-dm-cfg.bin {
102 filename = "combined-dm-cfg.bin";
A Dk3-am62a-sk-binman.dtsi11 config = "tifs-rm-cfg.yaml";
42 combined_tifs_cfg: combined-tifs-cfg.bin {
43 filename = "combined-tifs-cfg.bin";
50 combined_dm_cfg: combined-dm-cfg.bin {
51 filename = "combined-dm-cfg.bin";
86 combined_tifs_cfg_fs: combined-tifs-cfg.bin {
87 filename = "combined-tifs-cfg.bin";
94 combined_dm_cfg_fs: combined-dm-cfg.bin {
95 filename = "combined-dm-cfg.bin";
A Dk3-am67a-beagley-ai-u-boot.dtsi28 "cfg", "tchan", "rchan", "rflow";
93 combined_tifs_cfg: combined-tifs-cfg.bin {
94 filename = "combined-tifs-cfg.bin";
103 combined_dm_cfg: combined-dm-cfg.bin {
104 filename = "combined-dm-cfg.bin";
143 combined_tifs_cfg_fs: combined-tifs-cfg.bin {
144 filename = "combined-tifs-cfg.bin";
153 combined_dm_cfg_fs: combined-dm-cfg.bin {
154 filename = "combined-dm-cfg.bin";
A Dk3-j721s2-binman.dtsi38 combined_tifs_cfg: combined-tifs-cfg.bin {
39 filename = "combined-tifs-cfg.bin";
46 combined_dm_cfg: combined-dm-cfg.bin {
47 filename = "combined-dm-cfg.bin";
81 combined_tifs_cfg_fs: combined-tifs-cfg.bin {
82 filename = "combined-tifs-cfg.bin";
89 combined_dm_cfg_fs: combined-dm-cfg.bin {
90 filename = "combined-dm-cfg.bin";
124 filename = "combined-tifs-cfg.bin";
127 combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
[all …]
/arch/arm/cpu/armv7/ls102xa/
A Dfsl_ls1_serdes.c43 u32 cfg = in_be32(&gur->rcwsr[4]); in serdes_get_first_lane() local
49 cfg &= RCWSR4_SRDS1_PRTCL_MASK; in serdes_get_first_lane()
50 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; in serdes_get_first_lane()
55 cfg &= RCWSR4_SRDS2_PRTCL_MASK; in serdes_get_first_lane()
56 cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT; in serdes_get_first_lane()
64 if (unlikely(cfg == 0)) in serdes_get_first_lane()
68 if (serdes_get_prtcl(sd, cfg, i) == device) in serdes_get_first_lane()
79 u32 cfg; in serdes_init() local
83 cfg >>= sd_prctl_shift; in serdes_init()
84 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); in serdes_init()
[all …]
/arch/arm/mach-socfpga/
A Dclock_manager_s10.c46 if (cfg == 0) in cm_basic_init()
68 writel(cfg->main_pll_fdbck, in cm_basic_init()
72 writel(cfg->main_pll_pllc0, in cm_basic_init()
74 writel(cfg->main_pll_pllc1, in cm_basic_init()
76 writel(cfg->main_pll_nocdiv, in cm_basic_init()
95 writel(cfg->per_pll_fdbck, in cm_basic_init()
99 writel(cfg->per_pll_pllc0, in cm_basic_init()
101 writel(cfg->per_pll_pllc1, in cm_basic_init()
103 writel(cfg->per_pll_emacctl, in cm_basic_init()
105 writel(cfg->per_pll_gpiodiv, in cm_basic_init()
[all …]
A Dclock_manager_gen5.c146 writel(cfg->mpuclk, in cm_basic_init()
154 writel(cfg->mainclk, in cm_basic_init()
158 writel(cfg->dbgatclk, in cm_basic_init()
166 writel(cfg->emac0clk, in cm_basic_init()
170 writel(cfg->emac1clk, in cm_basic_init()
214 writel(cfg->maindiv, in cm_basic_init()
217 writel(cfg->dbgdiv, in cm_basic_init()
224 writel(cfg->perdiv, in cm_basic_init()
227 writel(cfg->gpiodiv, in cm_basic_init()
324 writel(cfg->persrc, in cm_basic_init()
[all …]
/arch/arm/cpu/armv8/fsl-layerscape/
A Dfsl_lsch3_serdes.c58 return cfg; in serdes_get_number()
90 u32 cfg = 0; in serdes_get_first_lane() local
120 cfg = serdes_get_number(sd, cfg); in serdes_get_first_lane()
123 if (cfg == 0) in serdes_get_first_lane()
138 u32 cfg; in serdes_init() local
147 cfg >>= sd_prctl_shift; in serdes_init()
149 cfg = serdes_get_number(sd, cfg); in serdes_init()
150 if (cfg == 0) { in serdes_init()
153 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); in serdes_init()
617 u32 cfg; in serdes_set_env() local
[all …]
A Dfsl_lsch2_serdes.c45 u32 cfg = gur_in32(&gur->rcwsr[4]); in serdes_get_first_lane() local
51 cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in serdes_get_first_lane()
57 cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in serdes_get_first_lane()
67 if (unlikely(cfg == 0)) in serdes_get_first_lane()
71 if (serdes_get_prtcl(sd, cfg, i) == device) in serdes_get_first_lane()
81 u32 cfg = gur_in32(&gur->rcwsr[4]) & in get_serdes_protocol() local
85 return cfg; in get_serdes_protocol()
106 u32 cfg; in serdes_init() local
115 cfg >>= sd_prctl_shift; in serdes_init()
116 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); in serdes_init()
[all …]
/arch/arm/mach-exynos/
A Dsystem.c36 unsigned int cfg = 0; in exynos4_set_system_display() local
43 cfg = readl(&sysreg->display_ctrl); in exynos4_set_system_display()
44 cfg |= (1 << 1); in exynos4_set_system_display()
45 writel(cfg, &sysreg->display_ctrl); in exynos4_set_system_display()
52 unsigned int cfg = 0; in exynos5_set_system_display() local
59 cfg = readl(&sysreg->disp1blk_cfg); in exynos5_set_system_display()
60 cfg |= (1 << 15); in exynos5_set_system_display()
61 writel(cfg, &sysreg->disp1blk_cfg); in exynos5_set_system_display()
A Dpower.c16 unsigned int addr, cfg = 0; in exynos4_mipi_phy_control() local
23 cfg = readl(addr); in exynos4_mipi_phy_control()
25 cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE); in exynos4_mipi_phy_control()
27 cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE); in exynos4_mipi_phy_control()
29 writel(cfg, addr); in exynos4_mipi_phy_control()
135 unsigned int cfg; in exynos5_dp_phy_control() local
139 cfg = readl(&power->dptx_phy_control); in exynos5_dp_phy_control()
141 cfg |= EXYNOS_DP_PHY_ENABLE; in exynos5_dp_phy_control()
143 cfg &= ~EXYNOS_DP_PHY_ENABLE; in exynos5_dp_phy_control()
145 writel(cfg, &power->dptx_phy_control); in exynos5_dp_phy_control()
/arch/arm/mach-stm32mp/stm32mp1/
A Dtzc400.c39 static uint16_t tzc_config_get_active_filters(const struct tzc_region *cfg) in tzc_config_get_active_filters() argument
43 for ( ; cfg->top != 0; cfg++) in tzc_config_get_active_filters()
44 active_filters |= cfg->filters_mask; in tzc_config_get_active_filters()
49 int tzc_configure(uintptr_t tzc, const struct tzc_region *cfg) in tzc_configure() argument
55 active_filters = tzc_config_get_active_filters(cfg); in tzc_configure()
63 for ( ; cfg->top != 0; cfg++, region += TZC_REGION_CFG_SIZE) { in tzc_configure()
64 attr_reg = (cfg->sec_mode & 0x03) << 30; in tzc_configure()
65 attr_reg |= (cfg->filters_mask & 0x03) << 0; in tzc_configure()
66 nsid = cfg->nsec_id & 0xffff; in tzc_configure()
69 tzc_write(region, TZC_REGION_BASE, cfg->base); in tzc_configure()
[all …]
/arch/powerpc/cpu/mpc85xx/
A Dfsl_corenet2_serdes.c125 u32 cfg = in_be32(&gur->rcwsr[4]); in serdes_get_first_lane() local
131 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in serdes_get_first_lane()
137 cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL; in serdes_get_first_lane()
143 cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL; in serdes_get_first_lane()
149 cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL; in serdes_get_first_lane()
158 if (unlikely(cfg == 0)) in serdes_get_first_lane()
162 if (serdes_get_prtcl(sd, cfg, i) == device) in serdes_get_first_lane()
196 u32 cfg; in serdes_init() local
331 cfg >>= sd_prctl_shift; in serdes_init()
332 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); in serdes_init()
[all …]
A Dfsl_corenet_serdes.c347 u32 devdisr, u32 devdisr2, int cfg) in p4080_erratum_serdes8() argument
369 switch (cfg) { in p4080_erratum_serdes8()
426 switch (cfg) { in p4080_erratum_serdes_a005()
454 int bank = serdes_get_bank_by_device(cfg, device); in p4080_erratum_serdes_a005()
494 int cfg; in fsl_serdes_init() local
533 if (!is_serdes_prtcl_valid(cfg)) { in fsl_serdes_init()
564 if ((cfg == 0xf) || (cfg == 0x10)) { in fsl_serdes_init()
591 switch (cfg) { in fsl_serdes_init()
693 lane_prtcl = serdes_get_prtcl(cfg, lane); in fsl_serdes_init()
821 p4080_erratum_serdes_a005(srds_regs, cfg); in fsl_serdes_init()
[all …]
/arch/arm/cpu/arm926ejs/mxs/
A Dspl_power_init.c1166 cfg->step_mV); in mxs_power_set_vddx()
1170 cur_target *= cfg->step_mV; in mxs_power_set_vddx()
1174 if (cfg->powered_by_linreg) in mxs_power_set_vddx()
1181 cfg->bo_enirq); in mxs_power_set_vddx()
1183 setbits_le32(cfg->reg, cfg->bo_offset_mask); in mxs_power_set_vddx()
1196 diff -= cfg->lowest_mV; in mxs_power_set_vddx()
1197 diff /= cfg->step_mV; in mxs_power_set_vddx()
1199 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff); in mxs_power_set_vddx()
1219 if (cfg->bo_irq) { in mxs_power_set_vddx()
1224 cfg->bo_enirq); in mxs_power_set_vddx()
[all …]
/arch/x86/lib/
A Dacpi_nhlt.c158 const struct nhlt_format_config *cfg = &formats[i]; in nhlt_endpoint_add_formats() local
164 fmt = nhlt_add_format(endp, cfg->num_channels, in nhlt_endpoint_add_formats()
165 cfg->sample_freq_khz, in nhlt_endpoint_add_formats()
166 cfg->container_bits_per_sample, in nhlt_endpoint_add_formats()
167 cfg->valid_bits_per_sample, in nhlt_endpoint_add_formats()
168 cfg->speaker_mask); in nhlt_endpoint_add_formats()
172 if (!cfg->settings_file) in nhlt_endpoint_add_formats()
178 cfg->settings_file); in nhlt_endpoint_add_formats()
200 return sizeof(cfg->size) + cfg->size; in calc_specific_config_size()
320 ser32(cur, cfg->size); in serialise_specific_config()
[all …]
/arch/arm/mach-apple/
A Dsart.c55 u32 cfg = readl(sart->base + APPLE_SART2_CONFIG(index)); in sart2_get_entry() local
56 *flags = FIELD_GET(APPLE_SART2_CONFIG_FLAGS, cfg); in sart2_get_entry()
57 *size = (size_t)FIELD_GET(APPLE_SART2_CONFIG_SIZE, cfg) << APPLE_SART2_CONFIG_SIZE_SHIFT; in sart2_get_entry()
65 u32 cfg; in sart2_set_entry() local
79 cfg = FIELD_PREP(APPLE_SART2_CONFIG_FLAGS, flags); in sart2_set_entry()
80 cfg |= FIELD_PREP(APPLE_SART2_CONFIG_SIZE, size); in sart2_set_entry()
83 writel(cfg, sart->base + APPLE_SART2_CONFIG(index)); in sart2_set_entry()
/arch/arm/mach-imx/
A Dcmd_nandbcb.c1062 struct boot_config cfg; in do_nandbcb_bcbonly() local
1078 mtd = cfg.mtd; in do_nandbcb_bcbonly()
1082 cfg.boot_stream1_size = ALIGN(cfg.boot_stream1_size, mtd->writesize); in do_nandbcb_bcbonly()
1087 cfg.boot_stream2_size = ALIGN(cfg.boot_stream2_size, in do_nandbcb_bcbonly()
1092 nandbcb_check_space(&cfg); in do_nandbcb_bcbonly()
1094 maxsize = cfg.maxsize; in do_nandbcb_bcbonly()
1095 off = cfg.offset; in do_nandbcb_bcbonly()
1115 fill_fcb(fcb, &cfg); in do_nandbcb_bcbonly()
1431 struct boot_config cfg; in do_nandbcb_dump() local
1447 ret = nandbcb_dump(&cfg); in do_nandbcb_dump()
[all …]
/arch/arm/include/asm/ti-common/
A Dti-edma3.h102 void qedma3_start(u32 base, struct edma3_channel_config *cfg);
103 void qedma3_stop(u32 base, struct edma3_channel_config *cfg);
104 void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg);
105 int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg);
/arch/mips/mach-mtmips/
A Dddr_init.c68 static void mc_ddr_init(void __iomem *memc, const struct mc_ddr_cfg *cfg, in mc_ddr_init() argument
79 writel(cfg->cfg2, memc + MEMCTL_DDR_CFG2_REG); in mc_ddr_init()
80 writel(cfg->cfg3, memc + MEMCTL_DDR_CFG3_REG); in mc_ddr_init()
81 writel(cfg->cfg4, memc + MEMCTL_DDR_CFG4_REG); in mc_ddr_init()
85 writel(cfg->cfg0, memc + MEMCTL_DDR_CFG0_REG); in mc_ddr_init()
87 val = cfg->cfg1; in mc_ddr_init()

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