Searched refs:cfg0 (Results 1 – 18 of 18) sorted by relevance
| /arch/mips/mach-mtmips/ |
| A D | ddr_init.c | 85 writel(cfg->cfg0, memc + MEMCTL_DDR_CFG0_REG); in mc_ddr_init()
203 static void mc_sdr_init(void __iomem *memc, mc_reset_t mc_reset, u32 cfg0, in mc_sdr_init() argument
210 writel(cfg0, memc + MEMCTL_SDRAM_CFG0_REG); in mc_sdr_init()
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| /arch/mips/mach-mtmips/include/mach/ |
| A D | ddr.h | 26 u32 cfg0; member
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| /arch/arm/mach-imx/ |
| A D | mmdc_size.c | 21 u32 cfg0; member
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| /arch/arm/include/asm/arch-sunxi/ |
| A D | tve.h | 31 u32 cfg0; /* 0x004 */ member
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| A D | dram_sun50i_h616.h | 47 u32 cfg0; /* 0x0 */ member
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| A D | dram_sun50i_h6.h | 52 u32 cfg0; /* 0x0 */ member
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| /arch/powerpc/cpu/mpc85xx/ |
| A D | fdt.c | 167 u32 cfg0 = in_be32(&cpc->cpccfg0); in ft_fixup_l3cache() local
169 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CFG_SYS_NUM_CPC; in ft_fixup_l3cache()
170 num_ways = CPC_CFG0_NUM_WAYS(cfg0); in ft_fixup_l3cache()
171 line_size = CPC_CFG0_LINE_SZ(cfg0); in ft_fixup_l3cache()
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| /arch/arm/mach-sunxi/ |
| A D | dram_sun50i_h6.c | 112 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0) in mbus_configure_port() local
120 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); in mbus_configure_port()
121 writel(cfg0, &mctl_com->master[port].cfg0); in mbus_configure_port()
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| A D | dram_sunxi_dw.c | 95 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0) in mbus_configure_port() local
103 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); in mbus_configure_port()
104 writel(cfg0, &mctl_com->mcr[port][0]); in mbus_configure_port()
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| A D | dram_sun50i_h616.c | 46 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0) in mbus_configure_port() local
54 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); in mbus_configure_port()
55 writel_relaxed(cfg0, &mctl_com->master[port].cfg0); in mbus_configure_port()
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| /arch/arm/mach-imx/mx7ulp/ |
| A D | soc.c | 427 serialnr->low = (fuse->cfg0 & 0xFFFF) + ((fuse->cfg1 & 0xFFFF) << 16); in get_board_serial()
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| /arch/powerpc/include/asm/ |
| A D | fsl_liodn.h | 228 offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
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| A D | immap_85xx.h | 2386 u32 cfg0; /* cfg register 0 */ member
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| /arch/arm/include/asm/arch-imx8m/ |
| A D | imx-regs.h | 205 u32 cfg0; member
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| /arch/mips/mach-octeon/ |
| A D | octeon_qlm.c | 4587 cvmx_gserx_lanex_tx_cfg_0_t cfg0; in octeon_configure_qlm_cn78xx() local
4593 cfg0.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_TX_CFG_0(l, qlm)); in octeon_configure_qlm_cn78xx()
4594 cfg0.s.cfg_tx_swing = 0x12; in octeon_configure_qlm_cn78xx()
4595 csr_wr_node(node, CVMX_GSERX_LANEX_TX_CFG_0(l, qlm), cfg0.u64); in octeon_configure_qlm_cn78xx()
5240 cvmx_gserx_lanex_tx_cfg_0_t cfg0; in octeon_configure_qlm_cn73xx() local
5248 cfg0.u64 = csr_rd(CVMX_GSERX_LANEX_TX_CFG_0(l, qlm)); in octeon_configure_qlm_cn73xx()
5249 cfg0.s.cfg_tx_swing = 0x12; in octeon_configure_qlm_cn73xx()
5250 csr_wr(CVMX_GSERX_LANEX_TX_CFG_0(l, qlm), cfg0.u64); in octeon_configure_qlm_cn73xx()
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| /arch/arm/include/asm/arch-mx7ulp/ |
| A D | imx-regs.h | 1014 u32 cfg0; member
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| /arch/arm/include/asm/arch-mx7/ |
| A D | imx-regs.h | 916 u32 cfg0; member
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| /arch/arm/dts/ |
| A D | ast2600.dtsi | 482 pcie_cfg0: cfg0@80 {
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