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Searched refs:ch (Results 1 – 25 of 32) sorted by relevance

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/arch/arm/include/asm/arch-rockchip/
A Dsdram.h47 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
49 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
50 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
52 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
54 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
56 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
58 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
60 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
62 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
83 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
A Dsdram_common.h283 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) argument
284 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) argument
285 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) argument
290 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) argument
292 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) argument
293 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + 16 * (ch))) & 0x3)) argument
296 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + 16 * (ch))) & 0x1)) argument
297 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) argument
298 #define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + 16 * (ch))) & 0x3)) argument
299 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) argument
[all …]
A Dsdram_rk3399.h77 struct rk3399_sdram_channel ch[2]; member
A Dsdram_px30.h126 struct px30_sdram_channel ch; member
A Dsdram_rk3328.h258 struct rk3328_sdram_channel ch; member
A Dsdram_rv1126.h332 struct rv1126_sdram_channel ch; member
/arch/x86/cpu/quark/
A Dsmc.c279 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
303 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
934 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
970 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1006 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1058 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1356 for (ch = 0; ch < NUM_CHANNELS; ch++) { in restore_timings()
1384 for (ch = 0; ch < NUM_CHANNELS; ch++) { in default_timings()
1445 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rcvn_cal()
1591 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_level()
[all …]
/arch/arm/mach-nexell/
A Dtimer.c46 #define TCFG0_BIT_CH(ch) ((ch) == 0 || (ch) == 1 ? 0 : 8) argument
47 #define TCFG1_BIT_CH(ch) ((ch) * 4) argument
48 #define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) argument
49 #define TINT_CH(ch) (ch) argument
50 #define TINT_CSTAT_BIT_CH(ch) ((ch) + 5) argument
80 writel(val | (0x1 << TINT_CSTAT_BIT_CH(ch) | on << ch), in timer_start()
96 writel(val | (0x1 << TINT_CSTAT_BIT_CH(ch) | on << ch), in timer_stop()
147 timer_stop(base, ch); in timer_init()
149 timer_count(base, ch, tcnt); in timer_init()
150 timer_start(base, ch); in timer_init()
[all …]
/arch/arm/mach-uniphier/clk/
A Dclk-ld11.c37 int ch; in uniphier_ld11_clk_init() local
39 for (ch = 0; ch < 3; ch++) { in uniphier_ld11_clk_init()
42 writel(0x82280600, phyctrl + 8 * ch); in uniphier_ld11_clk_init()
43 writel(0x00000106, phyctrl + 8 * ch + 4); in uniphier_ld11_clk_init()
/arch/arm/mach-rockchip/
A Dsdram.c353 u32 ch; in rockchip_sdram_size() local
370 for (ch = 0; ch < ch_num; ch++) { in rockchip_sdram_size()
378 bk = 3 + ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & in rockchip_sdram_size()
382 bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & in rockchip_sdram_size()
389 SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
394 SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
397 SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
401 SYS_REG_CS1_ROW_SHIFT(ch) & in rockchip_sdram_size()
406 SYS_REG_CS1_ROW_SHIFT(ch) & in rockchip_sdram_size()
409 SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) & in rockchip_sdram_size()
[all …]
/arch/arm/mach-uniphier/dram/
A Dumc-ld4.c41 static int umc_get_rank(int ch) in umc_get_rank() argument
43 return ch; /* ch0: rank0, ch1: rank1 for this SoC */ in umc_get_rank()
145 int freq, unsigned long size, bool ddr3plus, int ch) in umc_ch_init() argument
160 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
174 int ch, ret; in uniphier_ld4_umc_init() local
176 for (ch = 0; ch < DRAM_CH_NR; ch++) { in uniphier_ld4_umc_init()
178 bd->dram_ch[ch].size, in uniphier_ld4_umc_init()
179 !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch); in uniphier_ld4_umc_init()
181 pr_err("failed to initialize UMC ch%d\n", ch); in uniphier_ld4_umc_init()
A Dumc-sld8.c44 static int umc_get_rank(int ch) in umc_get_rank() argument
46 return ch; /* ch0: rank0, ch1: rank1 for this SoC */ in umc_get_rank()
148 int freq, unsigned long size, bool ddr3plus, int ch) in umc_ch_init() argument
163 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
177 int ch, ret; in uniphier_sld8_umc_init() local
179 for (ch = 0; ch < DRAM_CH_NR; ch++) { in uniphier_sld8_umc_init()
181 bd->dram_ch[ch].size, in uniphier_sld8_umc_init()
182 !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch); in uniphier_sld8_umc_init()
184 pr_err("failed to initialize UMC ch%d\n", ch); in uniphier_sld8_umc_init()
A Dumc-pxs2.c145 int ch) in ddrphy_init() argument
461 if (ch == 2) in umc_ud_init()
483 size, ch); in umc_dc_init()
528 if (ch != 2) { in umc_dc_init()
559 ddrphy_init(phy_base, freq, width, ch); in umc_ch_init()
573 umc_ud_init(umc_ch_base, ch); in umc_ch_init()
610 int ch, ret; in uniphier_pxs2_umc_init() local
624 for (ch = 0; ch < DRAM_CH_NR; ch++) { in uniphier_pxs2_umc_init()
625 unsigned long size = bd->dram_ch[ch].size; in uniphier_pxs2_umc_init()
626 unsigned int width = bd->dram_ch[ch].width; in uniphier_pxs2_umc_init()
[all …]
A Dumc-pro4.c168 int ch, ret; in uniphier_pro4_umc_init() local
170 for (ch = 0; ch < DRAM_CH_NR; ch++) { in uniphier_pro4_umc_init()
172 bd->dram_ch[ch].size, in uniphier_pro4_umc_init()
173 bd->dram_ch[ch].width, in uniphier_pro4_umc_init()
176 pr_err("failed to initialize UMC ch%d\n", ch); in uniphier_pro4_umc_init()
/arch/arm/mach-uniphier/bcu/
A Dbcu-ld4.c13 #define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) macro
27 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ in uniphier_ld4_bcu_init()
30 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ in uniphier_ld4_bcu_init()
33 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ in uniphier_ld4_bcu_init()
/arch/arm/mach-tegra/
A Divc.c101 struct tegra_ivc_channel_header *ch, in tegra_ivc_frame_pointer() argument
104 return (void *)tegra_ivc_frame_addr(ivc, ch, frame); in tegra_ivc_frame_pointer()
124 struct tegra_ivc_channel_header *ch) in tegra_ivc_channel_empty() argument
131 uint32_t w_count = READ_ONCE(ch->w_count); in tegra_ivc_channel_empty()
132 uint32_t r_count = READ_ONCE(ch->r_count); in tegra_ivc_channel_empty()
151 struct tegra_ivc_channel_header *ch) in tegra_ivc_channel_full() argument
157 return (READ_ONCE(ch->w_count) - READ_ONCE(ch->r_count)) >= in tegra_ivc_channel_full()
228 struct tegra_ivc_channel_header *ch) in tegra_ivc_channel_avail_count() argument
236 return READ_ONCE(ch->w_count) - READ_ONCE(ch->r_count); in tegra_ivc_channel_avail_count()
/arch/arm/dts/
A Dnuvoton-npcm750-evb.dts295 fan-tach-ch = /bits/ 8 <0x00 0x01>;
300 fan-tach-ch = /bits/ 8 <0x02 0x03>;
305 fan-tach-ch = /bits/ 8 <0x04 0x05>;
310 fan-tach-ch = /bits/ 8 <0x06 0x07>;
315 fan-tach-ch = /bits/ 8 <0x08 0x09>;
320 fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
325 fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
330 fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
A Dimx6q-dhcom-pdk2-u-boot.dtsi3 * Copyright (C) 2019 Claudius Heine <ch@denx.de>
A Dam335x-pdu001-u-boot.dtsi3 * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
A Dam335x-guardian-u-boot.dtsi3 * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
/arch/riscv/lib/
A Dsbi.c213 int sbi_dbcn_write_byte(unsigned char ch) in sbi_dbcn_write_byte() argument
219 ch, 0, 0, 0, 0, 0); in sbi_dbcn_write_byte()
231 void sbi_console_putchar(int ch) in sbi_console_putchar() argument
233 sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0); in sbi_console_putchar()
/arch/arm/mach-omap2/
A Dsec-common.c102 char *ch; in find_sig_start() local
106 ch = image_end - magic_str_len + 1; in find_sig_start()
107 if (!strncmp(ch, sig_start_magic, magic_str_len)) in find_sig_start()
108 return (u32)ch; in find_sig_start()
/arch/riscv/include/asm/
A Dsbi.h154 void sbi_console_putchar(int ch);
177 int sbi_dbcn_write_byte(unsigned char ch);
/arch/arm/mach-exynos/
A Ddmc_init_ddr3.c257 static bool dmc_valid_window_test_vector(int ch, int byte_lane) in dmc_valid_window_test_vector() argument
266 read_data = readl(test_addr + i * 4 + ch * 0x80); in dmc_valid_window_test_vector()
350 void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch, in test_shifts() argument
373 if (dmc_valid_window_test_vector(ch, byte_lane)) { in test_shifts()
402 int ch, unsigned int coarse_lock_val) in software_find_read_offset() argument
414 writel(test_pattern[i], test_addr + i * 4 + ch * 0x80); in software_find_read_offset()
423 test_shifts(phy_ctrl, ch, left_limit, right_limit, left); in software_find_read_offset()
424 test_shifts(phy_ctrl, ch, right_limit, left_limit, right); in software_find_read_offset()
/arch/arm/include/asm/mach-imx/
A Dregs-apbh.h36 } ch[8]; member
120 } ch[16]; member

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