| /arch/powerpc/dts/ |
| A D | elo3-dma-0.dtsi | 15 dma-channel@0 {
16 compatible = "fsl,eloplus-dma-channel";
20 dma-channel@80 {
21 compatible = "fsl,eloplus-dma-channel";
25 dma-channel@100 {
26 compatible = "fsl,eloplus-dma-channel";
30 dma-channel@180 {
35 dma-channel@300 {
40 dma-channel@380 {
45 dma-channel@400 {
[all …]
|
| A D | elo3-dma-1.dtsi | 15 dma-channel@0 {
16 compatible = "fsl,eloplus-dma-channel";
20 dma-channel@80 {
21 compatible = "fsl,eloplus-dma-channel";
25 dma-channel@100 {
26 compatible = "fsl,eloplus-dma-channel";
30 dma-channel@180 {
35 dma-channel@300 {
40 dma-channel@380 {
45 dma-channel@400 {
[all …]
|
| A D | km8321.dtsi | 73 dma-channel@0 {
74 compatible = "fsl,mpc8321-dma-channel",
75 "fsl,elo-dma-channel";
80 dma-channel@80 {
81 compatible = "fsl,mpc8321-dma-channel",
82 "fsl,elo-dma-channel";
87 dma-channel@100 {
88 compatible = "fsl,mpc8321-dma-channel",
89 "fsl,elo-dma-channel";
94 dma-channel@180 {
[all …]
|
| A D | pq3-dma-0.dtsi | 42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
|
| A D | pq3-dma-1.dtsi | 42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
|
| /arch/x86/cpu/quark/ |
| A D | mrc_util.c | 156 channel * DDRIODQ_CH_OFFSET; in set_rcvn()
172 channel * DDRIODQ_CH_OFFSET); in set_rcvn()
183 channel * DDRIODQ_CH_OFFSET; in set_rcvn()
228 channel * DDRIODQ_CH_OFFSET; in get_rcvn()
1000 if (channel > 0) { in get_addr()
1125 channel, rank, rcvn); in find_rising_edge()
1354 uint8_t channel; in clear_pointers() local
1359 for (channel = 0; channel < NUM_CHANNELS; channel++) { in clear_pointers()
1447 uint8_t channel; in print_timings() local
1456 for (channel = 0; channel < NUM_CHANNELS; channel++) { in print_timings()
[all …]
|
| A D | mrc_util.h | 87 void set_rcvn(uint8_t channel, uint8_t rank,
90 void set_rdqs(uint8_t channel, uint8_t rank,
93 void set_wdqs(uint8_t channel, uint8_t rank,
96 void set_wdq(uint8_t channel, uint8_t rank,
99 void set_wcmd(uint8_t channel, uint32_t pi_count);
100 uint32_t get_wcmd(uint8_t channel);
102 uint32_t get_wclk(uint8_t channel, uint8_t rank);
104 uint32_t get_wctl(uint8_t channel, uint8_t rank);
106 uint32_t get_vref(uint8_t channel, uint8_t byte_lane);
108 uint32_t get_addr(uint8_t channel, uint8_t rank);
[all …]
|
| /arch/mips/mach-octeon/ |
| A D | cvmx-helper-fdt.c | 170 channel = cvmx_fdt_alloc(sizeof(*channel) + in cvmx_fdt_parse_vsc7224_channels()
172 if (!channel) { in cvmx_fdt_parse_vsc7224_channels()
177 vsc7224->channel[reg] = channel; in cvmx_fdt_parse_vsc7224_channels()
179 channel->lane = reg; in cvmx_fdt_parse_vsc7224_channels()
181 channel->is_tx = is_tx; in cvmx_fdt_parse_vsc7224_channels()
194 __func__, i, channel->taps[i].len, channel->taps[i].main_tap, in cvmx_fdt_parse_vsc7224_channels()
195 channel->taps[i].pre_tap, channel->taps[i].post_tap); in cvmx_fdt_parse_vsc7224_channels()
198 channel->ipd_port = -1; in cvmx_fdt_parse_vsc7224_channels()
226 channel->xiface = xiface; in cvmx_fdt_parse_vsc7224_channels()
227 channel->index = index; in cvmx_fdt_parse_vsc7224_channels()
[all …]
|
| A D | cvmx-helper-ilk.c | 203 entry = 1 + channel + (channel / 15); in __cvmx_ilk_write_tx_cal_entry_cn68xx()
261 void __cvmx_ilk_write_tx_cal_entry_cn78xx(int intf, int channel, in __cvmx_ilk_write_tx_cal_entry_cn78xx() argument
265 int calender_16_block = channel / 15; in __cvmx_ilk_write_tx_cal_entry_cn78xx()
266 int calender_16_index = channel % 15 + 1; in __cvmx_ilk_write_tx_cal_entry_cn78xx()
280 tx_cal.s.channel = channel; in __cvmx_ilk_write_tx_cal_entry_cn78xx()
293 void __cvmx_ilk_write_tx_cal_entry(int interface, int channel, in __cvmx_ilk_write_tx_cal_entry() argument
306 int calender_16_block = channel / 15; in __cvmx_ilk_write_rx_cal_entry_cn78xx()
307 int calender_16_index = channel % 15 + 1; in __cvmx_ilk_write_rx_cal_entry_cn78xx()
321 rx_cal.s.channel = channel; in __cvmx_ilk_write_rx_cal_entry_cn78xx()
353 entry = 1 + channel + (channel / 15); in __cvmx_ilk_write_rx_cal_entry_cn68xx()
[all …]
|
| /arch/arm/mach-exynos/ |
| A D | dmc_common.c | 97 int channel, chip; in dmc_config_mrs() local
99 for (channel = 0; channel < mem->dmc_channels; channel++) { in dmc_config_mrs()
102 mask = channel << DIRECT_CMD_CHANNEL_SHIFT; in dmc_config_mrs()
138 int channel, chip; in dmc_config_prech() local
140 for (channel = 0; channel < mem->dmc_channels; channel++) { in dmc_config_prech()
143 mask = channel << DIRECT_CMD_CHANNEL_SHIFT; in dmc_config_prech()
|
| /arch/arm/dts/ |
| A D | ste-ab8500.dtsi | 58 #io-channel-cells = <1>;
61 bat_ctrl: channel@01 {
64 btemp_ball: channel@02 {
70 acc_detect1: channel@04 {
76 adc_aux1: channel@06 {
79 adc_aux2: channel@07 {
85 vbus_v: channel@09 {
94 bk_bat_v: channel@0c {
97 die_temp: channel@0d {
100 usb_id: channel@0e {
[all …]
|
| A D | ste-ab8505.dtsi | 54 #io-channel-cells = <1>;
57 bat_ctrl: channel@01 {
60 btemp_ball: channel@02 {
63 acc_detect1: channel@04 {
69 adc_aux1: channel@06 {
72 adc_aux2: channel@07 {
78 vbus_v: channel@09 {
81 charger_c: channel@0b {
84 bk_bat_v: channel@0c {
87 die_temp: channel@0d {
[all …]
|
| A D | imx6qdl-gw5907.dtsi | 166 channel@0 {
172 channel@2 {
178 channel@5 {
184 channel@8 {
190 channel@b {
196 channel@e {
202 channel@11 {
208 channel@14 {
305 channel@4 {
311 channel@5 {
[all …]
|
| A D | zynqmp-sc-vm-p-m1369-00-revA.dtso | 153 #io-channel-cells = <1>;
160 #io-channel-cells = <1>;
167 #io-channel-cells = <1>;
174 #io-channel-cells = <1>;
181 #io-channel-cells = <1>;
188 #io-channel-cells = <1>;
195 #io-channel-cells = <1>;
202 #io-channel-cells = <1>;
209 #io-channel-cells = <1>;
216 #io-channel-cells = <1>;
[all …]
|
| A D | imx6qdl-gw5913.dtsi | 151 channel@6 {
157 channel@8 {
163 channel@82 {
171 channel@84 {
178 channel@86 {
185 channel@88 {
192 channel@8c {
198 channel@8e {
204 channel@90 {
210 channel@92 {
[all …]
|
| A D | zynqmp-sc-vn-p-b2197-00-revA.dtso | 232 #io-channel-cells = <1>;
239 #io-channel-cells = <1>;
246 #io-channel-cells = <1>;
253 #io-channel-cells = <1>;
260 #io-channel-cells = <1>;
267 #io-channel-cells = <1>;
274 #io-channel-cells = <1>;
281 #io-channel-cells = <1>;
288 #io-channel-cells = <1>;
295 #io-channel-cells = <1>;
[all …]
|
| A D | imx6qdl-gw552x.dtsi | 156 channel@0 {
162 channel@2 {
168 channel@5 {
174 channel@8 {
180 channel@b {
186 channel@e {
192 channel@11 {
198 channel@14 {
204 channel@17 {
210 channel@1d {
[all …]
|
| A D | zynqmp-e-a2197-00-revA.dts | 262 #io-channel-cells = <1>;
270 #io-channel-cells = <1>;
278 #io-channel-cells = <1>;
286 #io-channel-cells = <1>;
294 #io-channel-cells = <1>;
302 #io-channel-cells = <1>;
322 #io-channel-cells = <1>;
330 #io-channel-cells = <1>;
338 #io-channel-cells = <1>;
346 #io-channel-cells = <1>;
[all …]
|
| A D | imx6qdl-gw5910.dtsi | 175 channel@6 {
181 channel@8 {
187 channel@82 {
195 channel@84 {
202 channel@86 {
209 channel@88 {
216 channel@8c {
222 channel@8e {
228 channel@90 {
234 channel@92 {
[all …]
|
| A D | imx6qdl-gw5912.dtsi | 171 channel@0 {
177 channel@2 {
183 channel@5 {
189 channel@8 {
195 channel@b {
201 channel@e {
207 channel@11 {
213 channel@14 {
219 channel@17 {
225 channel@1d {
[all …]
|
| A D | imx6qdl-gw53xx.dtsi | 222 channel@0 {
228 channel@2 {
234 channel@5 {
240 channel@8 {
246 channel@b {
252 channel@e {
258 channel@11 {
264 channel@14 {
270 channel@17 {
276 channel@1d {
[all …]
|
| A D | imx6qdl-gw51xx.dtsi | 166 channel@0 {
172 channel@2 {
178 channel@5 {
184 channel@8 {
190 channel@b {
196 channel@e {
202 channel@11 {
208 channel@14 {
214 channel@17 {
220 channel@1d {
[all …]
|
| A D | imx6qdl-gw52xx.dtsi | 229 channel@0 {
235 channel@2 {
241 channel@5 {
247 channel@8 {
253 channel@b {
259 channel@e {
265 channel@11 {
271 channel@14 {
277 channel@17 {
283 channel@1d {
[all …]
|
| /arch/mips/mach-octeon/include/mach/ |
| A D | cvmx-helper-ilk.h | 31 void __cvmx_ilk_write_tx_cal_entry(int interface, int channel, unsigned char bpid);
41 void __cvmx_ilk_write_rx_cal_entry(int interface, int channel, unsigned char pipe);
|
| /arch/arm/include/asm/arch-lpc32xx/ |
| A D | dma.h | 60 int lpc32xx_dma_start_xfer(unsigned int channel,
62 int lpc32xx_dma_wait_status(unsigned int channel);
|