| /arch/arm/mach-exynos/ |
| A D | dmc_common.c | 97 int channel, chip; in dmc_config_mrs() local
103 for (chip = 0; chip < mem->chips_to_configure; chip++) { in dmc_config_mrs()
106 mask |= chip << DIRECT_CMD_CHIP_SHIFT; in dmc_config_mrs()
138 int channel, chip; in dmc_config_prech() local
144 for (chip = 0; chip < mem->chips_per_channel; chip++) { in dmc_config_prech()
145 mask |= chip << DIRECT_CMD_CHIP_SHIFT; in dmc_config_prech()
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| A D | dmc_init_ddr3.c | 451 int chip; in ddr3_mem_ctrl_init() local
678 for (chip = 0; chip < mem->chips_to_configure; chip++) { in ddr3_mem_ctrl_init()
680 (chip << DIRECT_CMD_CHIP_SHIFT), in ddr3_mem_ctrl_init()
683 (chip << DIRECT_CMD_CHIP_SHIFT), in ddr3_mem_ctrl_init()
722 for (chip = 0; chip < mem->chips_to_configure; chip++) { in ddr3_mem_ctrl_init()
723 writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), in ddr3_mem_ctrl_init()
725 writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), in ddr3_mem_ctrl_init()
777 for (chip = 0; chip < mem->chips_to_configure; chip++) { in ddr3_mem_ctrl_init()
778 writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), in ddr3_mem_ctrl_init()
780 writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), in ddr3_mem_ctrl_init()
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| A D | dmc_init_exynos4.c | 66 static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip) in dmc_config_mrs() argument
71 if (chip) in dmc_config_mrs()
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| /arch/mips/mach-ath79/ |
| A D | cpu.c | 16 const char *chip; member
107 const char *chip = "????"; in print_cpuinfo() local
113 chip = desc[i].chip; in print_cpuinfo()
128 printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip, in print_cpuinfo()
132 printf("Qualcomm Atheros TP%s rev %u\n", chip, rev); in print_cpuinfo()
138 printf("Atheros AR%s rev %u\n", chip, rev); in print_cpuinfo()
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| /arch/arm/dts/ |
| A D | uniphier-ld6b.dtsi | 9 * LD6b consists of two silicon dies: D-chip and A-chip.
10 * The D-chip (digital chip) is the same as the PXs2 die.
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| A D | rk3399-roc-pc-u-boot.dtsi | 3 * Copyright (C) 2019 Levin Du <djw@t-chip.com.cn>
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| A D | socfpga_cyclone5_vining_fpga.dts | 221 reg = <0>; /* chip select */
238 reg = <1>; /* chip select */
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| A D | socfpga_cyclone5_sr1500.dts | 100 reg = <0>; /* chip select */
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| A D | socfpga_cyclone5_is1.dts | 92 reg = <0>; /* chip select */
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| A D | an7581-u-boot.dtsi | 34 compatible = "airoha,en7581-chip-scu", "syscon";
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| A D | socfpga_cyclone5_socdk.dts | 128 reg = <0>; /* chip select */
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| A D | sun50i-a64-sopine.dtsi | 124 * The A64 chip cannot work without this regulator off, although
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| A D | sun8i-r16-parrot.dts | 234 * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered.
245 * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered.
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| A D | vexpress-v2p-ca9.dts | 192 /* ACLK clock to the AXI master port on the test chip */
210 /* Reference clock for the test chip internal PLLs */
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| /arch/arm/include/asm/arch-bcmns3/ |
| A D | bl33_info.h | 21 struct chip_info chip; member
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| /arch/arm/include/asm/arch-vf610/ |
| A D | gpio.h | 24 unsigned int chip; member
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| /arch/arm/mach-aspeed/ast2500/ |
| A D | Kconfig | 9 Evb-AST2500 is Aspeed evaluation board for AST2500 chip.
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| /arch/arm/mach-aspeed/ast2600/ |
| A D | Kconfig | 10 EVB-AST2600 is Aspeed evaluation board for AST2600A0 chip.
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| /arch/arm/mach-airoha/ |
| A D | Kconfig | 15 crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder,
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| /arch/arm/mach-tegra/ |
| A D | cpu.c | 217 int chip = tegra_get_chip(); in pllx_set_rate() local
235 if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) in pllx_set_rate()
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| /arch/arm/mach-mediatek/ |
| A D | Kconfig | 27 crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder,
111 chip and several DDR3 and DDR4 options.
120 chip and several DDR3 and DDR4 options.
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| /arch/arm/mach-imx/ |
| A D | Kconfig | 159 chip to the OEM's server.
170 bool "Enable DDRMC (DDR3) on-chip calibration"
173 Vybrid (vf610) SoC provides some on-chip facility to tune the DDR3
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| /arch/mips/dts/ |
| A D | mrvl,cn73xx.dtsi | 37 /* The chip select number and offset */
39 /* The size of the chip select region */
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| A D | mscc,servalt.dtsi | 101 compatible = "mscc,servalt-chip-reset";
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| /arch/arm/mach-omap2/omap3/ |
| A D | Kconfig | 142 ID and MFR of the first attached NAND chip, if present.
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