Searched refs:clk_sel (Results 1 – 3 of 3) sorted by relevance
| /arch/x86/cpu/apollolake/ |
| A D | uart.c | 38 u32 clk_sel; in lpss_clk_update() local
40 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
42 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
44 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
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| /arch/arm/mach-imx/mx5/ |
| A D | clock.c | 324 static u32 get_standard_pll_sel_clk(u32 clk_sel) in get_standard_pll_sel_clk() argument
328 switch (clk_sel & 0x3) { in get_standard_pll_sel_clk()
351 unsigned int clk_sel, freq, reg, pred, podf; in get_uart_clk() local
354 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg); in get_uart_clk()
355 freq = get_standard_pll_sel_clk(clk_sel); in get_uart_clk()
370 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq; in imx_get_cspiclk() local
377 freq = get_standard_pll_sel_clk(clk_sel); in imx_get_cspiclk()
387 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0; in get_esdhc_clk() local
799 s32 shift = 0, clk_sel, div = 1; in config_ddr_clk() local
810 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); in config_ddr_clk()
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| /arch/arm/mach-imx/mx6/ |
| A D | clock.c | 1045 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0; in get_usdhc_clk() local
1063 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL; in get_usdhc_clk()
1069 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL; in get_usdhc_clk()
1075 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL; in get_usdhc_clk()
1081 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL; in get_usdhc_clk()
1088 if (clk_sel) in get_usdhc_clk()
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