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Searched refs:clkctrl (Results 1 – 14 of 14) sorted by relevance

/arch/arm/cpu/arm926ejs/mxs/
A Dclock.c41 uint32_t clkctrl, clkseq, div; in mxs_get_pclk() local
47 if (clkctrl & in mxs_get_pclk()
64 div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK; in mxs_get_pclk()
74 uint32_t clkctrl; in mxs_get_hclk() local
79 if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN) in mxs_get_hclk()
82 div = clkctrl & CLKCTRL_HBUS_DIV_MASK; in mxs_get_hclk()
91 uint32_t clkctrl, clkseq, div; in mxs_get_emiclk() local
107 div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK; in mxs_get_emiclk()
122 uint32_t clkctrl, clkseq, div; in mxs_get_gpmiclk() local
130 div = clkctrl & CLKCTRL_GPMI_DIV_MASK; in mxs_get_gpmiclk()
[all …]
/arch/arm/mach-omap2/am33xx/
A Dclock.c122 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; in wait_for_clk_enable() local
127 clkctrl = readl(clkctrl_addr); in wait_for_clk_enable()
128 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> in wait_for_clk_enable()
132 clkctrl_addr, clkctrl); in wait_for_clk_enable()
150 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL; in wait_for_clk_disable() local
154 clkctrl = readl(clkctrl_addr); in wait_for_clk_disable()
155 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> in wait_for_clk_disable()
159 clkctrl_addr, clkctrl); in wait_for_clk_disable()
A Dclock_am43xx.c54 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; in setup_clocks_for_console() local
69 clkctrl = readl(&cmwkup->wkup_uart0ctrl); in setup_clocks_for_console()
70 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> in setup_clocks_for_console()
/arch/mips/dts/
A Dmt7620.dtsi34 clkctrl: clkctrl@10000030 { label
61 clocks = <&clkctrl CLK_UARTF>;
78 clocks = <&clkctrl CLK_UARTL>;
234 clocks = <&clkctrl CLK_SPI>;
250 clocks = <&clkctrl CLK_EPHY>,
251 <&clkctrl CLK_ESW>,
252 <&clkctrl CLK_FE>;
265 clocks = <&clkctrl CLK_UPHY_48M>, <&clkctrl CLK_UPHY_12M>;
289 clocks = <&clk48m>, <&clkctrl CLK_SDHC>;
A Dmt7628a.dtsi56 clkctrl: clkctrl@0x2c { label
304 clocks = <&clkctrl CLK_SPI>;
314 clocks = <&clkctrl CLK_UART0>;
332 clocks = <&clkctrl CLK_UART1>;
350 clocks = <&clkctrl CLK_UART2>;
384 clocks = <&clkctrl CLK_UPHY>;
405 clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
A Dmt7621.dtsi54 clkctrl: clock-controller@1e000030 { label
192 clocks = <&clkctrl MT7621_CLK_SPI>;
205 clocks = <&clkctrl MT7621_CLK_UART1>;
219 clocks = <&clkctrl MT7621_CLK_UART2>;
235 clocks = <&clkctrl MT7621_CLK_UART3>;
255 clocks = <&clkctrl MT7621_CLK_GDMA>,
256 <&clkctrl MT7621_CLK_ETH>;
286 clocks = <&clk50m>, <&clkctrl MT7621_CLK_SHXC>;
A Dmt7628-u-boot.dtsi16 &clkctrl {
A Dmt7621-u-boot.dtsi24 &clkctrl {
/arch/arm/dts/
A Dam33xx-clocks.dtsi547 compatible = "ti,clkctrl";
553 compatible = "ti,clkctrl";
559 compatible = "ti,clkctrl";
565 compatible = "ti,clkctrl";
571 compatible = "ti,clkctrl";
577 compatible = "ti,clkctrl";
583 compatible = "ti,clkctrl";
589 compatible = "ti,clkctrl";
603 compatible = "ti,clkctrl";
609 compatible = "ti,clkctrl";
[all …]
A Dimx23.dtsi488 clks: clkctrl@80040000 {
489 compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
A Dimx28.dtsi1110 clks: clkctrl@80040000 {
1111 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
/arch/arm/mach-omap2/
A Dclocks-common.c680 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; in wait_for_clk_enable() local
686 clkctrl = readl(clkctrl_addr); in wait_for_clk_enable()
687 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> in wait_for_clk_enable()
691 clkctrl_addr, clkctrl); in wait_for_clk_enable()
709 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL; in wait_for_clk_disable() local
713 clkctrl = readl(clkctrl_addr); in wait_for_clk_disable()
714 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> in wait_for_clk_disable()
718 clkctrl_addr, clkctrl); in wait_for_clk_disable()
A Demif-common.c1469 u32 val, i, clkctrl; in do_bug0039_workaround() local
1482 clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); in do_bug0039_workaround()
1500 __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); in do_bug0039_workaround()
/arch/arm/mach-exynos/include/mach/
A Ddsim.h17 unsigned int clkctrl; member

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