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/arch/arm/dts/
A Dam33xx-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
20 clock-mult = <1>;
21 clock-div = <1>;
28 clock-mult = <1>;
29 clock-div = <1>;
36 clock-mult = <1>;
37 clock-div = <1>;
45 clock-div = <1>;
53 clock-div = <1>;
[all …]
A Dam43xx-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
36 clock-mult = <1>;
37 clock-div = <1>;
44 clock-mult = <1>;
45 clock-div = <1>;
53 clock-div = <1>;
61 clock-div = <1>;
69 clock-div = <1>;
77 clock-div = <1>;
[all …]
A Ddra7xx-clocks.dtsi9 #clock-cells = <0>;
15 #clock-cells = <0>;
21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
[all …]
A Domap3xxx-clocks.dtsi9 #clock-cells = <0>;
15 #clock-cells = <0>;
22 #clock-cells = <0>;
43 clock-mult = <2>;
44 clock-div = <1>;
51 clock-mult = <2>;
52 clock-div = <1>;
59 clock-mult = <2>;
60 clock-div = <1>;
68 clock-div = <1>;
[all …]
A Domap36xx-omap3430es2plus-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
26 #clock-cells = <0>;
35 clock-mult = <1>;
36 clock-div = <2>;
51 clock-mult = <1>;
52 clock-div = <1>;
76 clock-div = <2>;
84 clock-div = <2>;
92 clock-div = <4>;
[all …]
A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi9 #clock-cells = <0>;
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
20 clock-mult = <1>;
21 clock-div = <5>;
56 clock-div = <3>;
64 clock-div = <4>;
72 clock-div = <6>;
80 clock-div = <1>;
[all …]
A Djuno-clocks.dtsi13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <7372800>;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
41 compatible = "fixed-clock";
[all …]
A Domap34xx-omap36xx-clocks.dtsi9 #clock-cells = <0>;
12 clock-mult = <1>;
13 clock-div = <1>;
17 #clock-cells = <0>;
25 #clock-cells = <0>;
33 #clock-cells = <0>;
41 #clock-cells = <0>;
77 clock-mult = <1>;
78 clock-div = <1>;
126 clock-div = <1>;
[all …]
A Dsama5d2.dtsi19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <0>;
26 #clock-cells = <0>;
27 clock-frequency = <0>;
131 #clock-cells = <0>;
137 #clock-cells = <0>;
148 #clock-cells = <0>;
154 #clock-cells = <0>;
160 #clock-cells = <0>;
[all …]
A Dimx7ulp.dtsi8 #include <dt-bindings/clock/imx7ulp-clock.h>
55 rosc: clock-rosc {
59 #clock-cells = <0>;
62 sosc: clock-sosc {
66 #clock-cells = <0>;
69 sirc: clock-sirc {
73 #clock-cells = <0>;
76 firc: clock-firc {
80 #clock-cells = <0>;
83 upll: clock-upll {
[all …]
A Domap36xx-clocks.dtsi9 #clock-cells = <0>;
16 #clock-cells = <0>;
26 #clock-cells = <0>;
35 #clock-cells = <0>;
44 #clock-cells = <0>;
53 #clock-cells = <0>;
62 #clock-cells = <0>;
71 clock-mult = <1>;
75 clock-mult = <1>;
79 ti,clock-mult = <1>;
[all …]
A Dexynos7420.dtsi11 #include <dt-bindings/clock/exynos7420-clk.h>
16 compatible = "fixed-clock";
17 clock-output-names = "fin_pll";
19 #clock-cells = <0>;
22 clock_topc: clock-controller@10570000 {
23 compatible = "samsung,exynos7-clock-topc";
26 #clock-cells = <1>;
28 clock-names = "fin_pll";
31 clock_top0: clock-controller@105d0000 {
35 #clock-cells = <1>;
[all …]
A Dimx8ulp.dtsi6 #include <dt-bindings/clock/imx8ulp-clock.h>
87 frosc: clock-frosc {
91 #clock-cells = <0>;
94 lposc: clock-lposc {
98 #clock-cells = <0>;
101 rosc: clock-rosc {
105 #clock-cells = <0>;
108 sosc: clock-sosc {
112 #clock-cells = <0>;
199 #clock-cells = <1>;
[all …]
A Drtsm_ve-motherboard.dtsi12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <24000000>;
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <32768>;
45 /* CLCD clock */
49 #clock-cells = <0>;
[all …]
A Dsc5xx.dtsi7 #include <dt-bindings/clock/adi-sc5xx-clock.h>
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <25000000>;
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <25000000>;
47 #clock-cells = <1>;
49 clock-names = "sys_clkin0", "sys_clkin1";
A Dmt7623.dtsi72 #clock-cells = <0>;
77 #clock-cells = <0>;
84 #clock-cells = <0>;
103 #clock-cells = <1>;
109 #clock-cells = <1>;
115 #clock-cells = <1>;
168 #clock-cells = <1>;
249 #clock-cells = <1>;
332 clock-names = "ref";
429 #clock-cells = <1>;
[all …]
A Dcorstone1000.dtsi70 compatible = "fixed-clock";
71 #clock-cells = <0>;
78 compatible = "fixed-clock";
79 #clock-cells = <0>;
80 clock-frequency = <48000000>;
81 clock-output-names = "smclk";
97 /* UART clock - 50MHz */
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
156 clock-names = "apb_pclk";
[all …]
A Dimx8ulp-evk.dts23 clock_ext_rmii: clock-ext-rmii {
24 compatible = "fixed-clock";
25 clock-frequency = <50000000>;
26 clock-output-names = "ext_rmii_clk";
27 #clock-cells = <0>;
30 clock_ext_ts: clock-ext-ts {
31 compatible = "fixed-clock";
33 clock-frequency = <50000000>;
34 clock-output-names = "ext_ts_clk";
35 #clock-cells = <0>;
[all …]
A Dste-dbx5x0-u-boot.dtsi9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <100000000>;
16 clock-frequency = <133000000>;
19 clock = <38400000>;
22 clock = <38400000>;
25 clock = <38400000>;
/arch/arm/mach-socfpga/
A Dclock_manager_gen5.c345 u32 reg, clock; in cm_get_main_vco_clk_hz() local
355 return clock; in cm_get_main_vco_clk_hz()
380 return clock; in cm_get_per_vco_clk_hz()
394 return clock; in cm_get_mpu_clk_hz()
425 return clock; in cm_get_sdram_clk_hz()
460 clock = clock / (1 << reg); in cm_get_l4_sp_clk_hz()
462 return clock; in cm_get_l4_sp_clk_hz()
493 clock /= 4; in cm_get_mmc_controller_clk_hz()
494 return clock; in cm_get_mmc_controller_clk_hz()
524 return clock; in cm_get_qspi_controller_clk_hz()
[all …]
A Dclock_manager_s10.c266 clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; in cm_get_mpu_clk_hz()
268 switch (clock) { in cm_get_mpu_clk_hz()
298 return clock; in cm_get_mpu_clk_hz()
306 clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; in cm_get_l3_main_clk_hz()
308 switch (clock) { in cm_get_l3_main_clk_hz()
337 return clock; in cm_get_l3_main_clk_hz()
345 clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; in cm_get_mmc_controller_clk_hz()
347 switch (clock) { in cm_get_mmc_controller_clk_hz()
374 return clock / 4; in cm_get_mmc_controller_clk_hz()
384 return clock; in cm_get_l4_sp_clk_hz()
[all …]
/arch/nios2/dts/
A D10m50_devboard.dts39 clock-frequency = <75000000>;
136 enet_pll: clock@0 {
138 #clock-cells = <1>;
142 #clock-cells = <0>;
149 #clock-cells = <0>;
156 #clock-cells = <0>;
162 sys_pll: clock@1 {
164 #clock-cells = <1>;
168 #clock-cells = <0>;
175 #clock-cells = <0>;
[all …]
/arch/arc/dts/
A Demsdp.dts21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <40000000>;
30 clock-frequency = <100000000>;
37 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
39 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <100000000>;
45 #clock-cells = <0>;
[all …]
A Diot_devkit.dts19 #clock-cells = <0>;
20 compatible = "fixed-clock";
21 clock-frequency = <144000000>;
28 clock-frequency = <16000000>;
47 compatible = "fixed-clock";
48 clock-frequency = <50000000>;
49 #clock-cells = <0>;
53 compatible = "fixed-clock";
54 clock-frequency = <50000000>;
55 #clock-cells = <0>;
[all …]
A Daxs10x_mb.dtsi23 compatible = "fixed-clock";
24 clock-frequency = <50000000>;
25 #clock-cells = <0>;
29 compatible = "fixed-clock";
31 #clock-cells = <0>;
36 compatible = "fixed-clock";
45 #clock-cells = <0>;
49 compatible = "fixed-clock";
51 #clock-cells = <0>;
61 clock-names = "stmmaceth";
[all …]

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