| /arch/arm/mach-tegra/ |
| A D | clock.c | 627 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) in clock_set_rate() function
875 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); in tegra30_set_up_pllp()
876 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); in tegra30_set_up_pllp()
880 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); in tegra30_set_up_pllp()
881 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in tegra30_set_up_pllp()
886 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); in tegra30_set_up_pllp()
887 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in tegra30_set_up_pllp()
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| /arch/arm/mach-tegra/tegra20/ |
| A D | clock.c | 630 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8); in clock_early_init()
631 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
635 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8); in clock_early_init()
636 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
640 clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8); in clock_early_init()
641 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
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| /arch/arm/mach-tegra/tegra210/ |
| A D | clock.c | 1016 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
1017 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); in clock_early_init()
1021 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
1022 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); in clock_early_init()
1027 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
1028 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); in clock_early_init()
1031 clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0); in clock_early_init()
1032 clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12); in clock_early_init()
1035 clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0); in clock_early_init()
1036 clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0); in clock_early_init()
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| /arch/arm/mach-tegra/tegra114/ |
| A D | clock.c | 712 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
713 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); in clock_early_init()
717 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
718 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); in clock_early_init()
723 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
724 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); in clock_early_init()
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| /arch/arm/mach-tegra/tegra124/ |
| A D | clock.c | 895 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); in clock_early_init()
896 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); in clock_early_init()
900 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); in clock_early_init()
901 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); in clock_early_init()
906 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); in clock_early_init()
907 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); in clock_early_init()
1175 clock_set_rate(CLOCK_ID_DISPLAY, best_n, best_m, best_p, cpcon); in clock_set_display_rate()
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| /arch/arm/include/asm/arch-tegra/ |
| A D | clock.h | 394 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
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| /arch/arm/mach-tegra/tegra30/ |
| A D | clock.c | 690 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); in clock_early_init()
694 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); in clock_early_init()
699 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); in clock_early_init()
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