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Searched refs:control (Results 1 – 25 of 158) sorted by relevance

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/arch/arm/dts/
A Dzynqmp-zcu1285-revA.dts58 rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */
60 txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */
61 rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */
62 rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */
63 rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */
64 rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */
65 rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */
66 txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */
67 txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */
68 txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */
[all …]
A Dzynqmp-zcu1275-revB.dts52 rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */
54 txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */
55 rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */
56 rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */
57 rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */
58 rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */
59 rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */
60 txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */
61 txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */
62 txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */
[all …]
A Dam4372-u-boot.dtsi14 compatible = "ti,control-phy-usb2-am437", "syscon";
18 compatible = "ti,control-phy-usb2-am437", "syscon";
A Dfsl-ls1088a-qds.dtsi40 #mux-control-cells = <1>;
123 fpga: board-control@3,0 {
A Dbcm2837-rpi-3-a-plus.dts134 * SDHCI is used to control the SDIO for wireless
137 * by a single GPIO. We can't give GPIO control to one of the drivers,
A Dexynos5800-peach-pi.dts241 ti,enable-ext-control;
244 ti,enable-ext-control;
247 ti,enable-ext-control;
A Darmada-388.dtsi11 * property and the name of the SoC, and add the second SATA host which control
/arch/arm/mach-imx/
A Dtimer.c20 unsigned int control; member
71 __raw_writel(GPTCR_SWR, &cur_gpt->control); in timer_init()
75 __raw_writel(0, &cur_gpt->control); in timer_init()
77 i = __raw_readl(&cur_gpt->control); in timer_init()
103 __raw_writel(i, &cur_gpt->control); in timer_init()
/arch/arm/mach-lpc32xx/
A Ddram.c55 writel(0x00000193, &emc->control); in ddr_init()
58 writel(0x00000113, &emc->control); in ddr_init()
66 writel(0x00000093, &emc->control); in ddr_init()
69 writel(0x00000093, &emc->control); in ddr_init()
72 writel(0x00000010, &emc->control); in ddr_init()
/arch/arm/mach-omap2/
A Dabb.c58 void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, in abb_setup() argument
64 if (!setup || !control || !txdone) in abb_setup()
100 writel(0, control); in abb_setup()
112 setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK); in abb_setup()
/arch/arm/cpu/armv7/
A Dsctlr.S18 mrc p15, 0, r0, c1, c0, 0 @ load system control register
20 mcr p15, 0, r0, c1, c0, 0 @ write system control register
A Dstart.S210 mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
212 mcr p15, 0, r0, c1, c0, 1 @ write auxilary control register
241 mrc p15, 0, r0, c1, c0, 0 @ read system control register
243 mcr p15, 0, r0, c1, c0, 0 @ write system control register
317 mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
329 mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
/arch/arm/cpu/arm11/
A Dsctlr.S20 mrc p15, 0, r0, c1, c0, 0 @ load system control register
23 mcr p15, 0, r0, c1, c0, 0 @ write system control register
/arch/arm/mach-npcm/npcm7xx/
A Dl2_cache_pl310_init.S32 STR r1, [r0,#0x104] @ auxilary control reg at offset 0x104
39 STR r1, [r0,#0x108] @ tag ram control reg at offset 0x108
46 STR r1, [r0,#0x10C] @ data ram control reg at offset 0x108
/arch/arm/mach-k3/r5/
A Dcommon.c271 region.control = region.control & ~0xF; in remove_fwl_region()
301 if (region.control != 0 && in remove_fwl_regions()
302 ((region.control >> K3_FIREWALL_BACKGROUND_BIT) & 1) == fwl_type) { in remove_fwl_regions()
305 region.control = 0; in remove_fwl_regions()
/arch/arm/include/asm/arch-lpc32xx/
A Demc.h17 u32 control; /* Controls dyn memory operation */ member
53 u32 control; /* Control register for AHB */ member
/arch/arm/include/asm/arch-tegra/
A Dpwm.h13 uint control; /* Control register */ member
A Dtegra_i2c.h75 struct i2c_control control; /* 60 ~ 78 */ member
94 struct i2c_control control; /* 50 ~ 68 */ member
/arch/powerpc/dts/
A Dqoriq-clockgen1.dtsi3 * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
A Dqoriq-clockgen2.dtsi3 * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
/arch/x86/include/asm/acpi/
A Dpci_osc.asl12 /* Let OS control everything */
/arch/x86/include/asm/arch-apollolake/acpi/
A Dscs.asl8 /* 0x600- is the dynamic clock gating control register offset (GENR) */
20 /* SCC power gate control method, this method must be serialized as
21 * multiple device will control the GENR register
/arch/arm/mach-davinci/include/mach/
A Dda8xx-usb.h31 dv_reg control; member
/arch/arm/include/asm/arch-omap3/
A Ddss.h44 u32 control; /* 0x40 */ member
58 u32 control; /* 0x40 */ member
/arch/x86/include/asm/acpi/dptf/
A Dfan.asl37 /* Fill in TFST with current control. */

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