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/arch/arm/mach-exynos/
A Ddmc_init_exynos4.c40 .control0 = CONTROL0_VAL,
59 writel((mem.control0 | (0 << mem.dll_on)), in phy_control_reset()
61 writel((mem.control0 | (1 << mem.dll_on)), in phy_control_reset()
108 writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0); in dmc_init()
A Dexynos4_setup.h397 unsigned control0; member

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