1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2021 NXP
5 */
6
7 #include <cpu_func.h>
8 #include <init.h>
9 #include <net.h>
10 #include <vsprintf.h>
11 #include <asm/arch/clock.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <asm/arch/immap_ls102xa.h>
15 #include <asm/cache.h>
16 #include <asm/system.h>
17 #include <tsec.h>
18 #include <netdev.h>
19 #include <fsl_esdhc.h>
20 #include <config.h>
21 #include <fsl_wdog.h>
22 #include <linux/delay.h>
23 #include <dm.h>
24
25 #include "fsl_epu.h"
26
27 #define DCSR_RCPM2_BLOCK_OFFSET 0x223000
28 #define DCSR_RCPM2_CPMFSMCR0 0x400
29 #define DCSR_RCPM2_CPMFSMSR0 0x404
30 #define DCSR_RCPM2_CPMFSMCR1 0x414
31 #define DCSR_RCPM2_CPMFSMSR1 0x418
32 #define CPMFSMSR_FSM_STATE_MASK 0x7f
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
37
38 /*
39 * Bit[1] of the descriptor indicates the descriptor type,
40 * and bit[0] indicates whether the descriptor is valid.
41 */
42 #define PMD_TYPE_TABLE 0x3
43 #define PMD_TYPE_SECT 0x1
44
45 /* AttrIndx[2:0] */
46 #define PMD_ATTRINDX(t) ((t) << 2)
47
48 /* Section */
49 #define PMD_SECT_AF (1 << 10)
50
51 #define BLOCK_SIZE_L1 (1UL << 30)
52 #define BLOCK_SIZE_L2 (1UL << 21)
53
54 /* TTBCR flags */
55 #define TTBCR_EAE (1 << 31)
56 #define TTBCR_T0SZ(x) ((x) << 0)
57 #define TTBCR_T1SZ(x) ((x) << 16)
58 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
59 #define TTBCR_IRGN0_NC (0 << 8)
60 #define TTBCR_IRGN0_WBWA (1 << 8)
61 #define TTBCR_IRGN0_WT (2 << 8)
62 #define TTBCR_IRGN0_WBNWA (3 << 8)
63 #define TTBCR_IRGN0_MASK (3 << 8)
64 #define TTBCR_ORGN0_NC (0 << 10)
65 #define TTBCR_ORGN0_WBWA (1 << 10)
66 #define TTBCR_ORGN0_WT (2 << 10)
67 #define TTBCR_ORGN0_WBNWA (3 << 10)
68 #define TTBCR_ORGN0_MASK (3 << 10)
69 #define TTBCR_SHARED_NON (0 << 12)
70 #define TTBCR_SHARED_OUTER (2 << 12)
71 #define TTBCR_SHARED_INNER (3 << 12)
72 #define TTBCR_EPD0 (0 << 7)
73 #define TTBCR (TTBCR_SHARED_NON | \
74 TTBCR_ORGN0_NC | \
75 TTBCR_IRGN0_NC | \
76 TTBCR_USING_TTBR0 | \
77 TTBCR_EAE)
78
79 /*
80 * Memory region attributes for LPAE (defined in pgtable):
81 *
82 * n = AttrIndx[2:0]
83 *
84 * n MAIR
85 * UNCACHED 000 00000000
86 * BUFFERABLE 001 01000100
87 * DEV_WC 001 01000100
88 * WRITETHROUGH 010 10101010
89 * WRITEBACK 011 11101110
90 * DEV_CACHED 011 11101110
91 * DEV_SHARED 100 00000100
92 * DEV_NONSHARED 100 00000100
93 * unused 101
94 * unused 110
95 * WRITEALLOC 111 11111111
96 */
97 #define MT_MAIR0 0xeeaa4400
98 #define MT_MAIR1 0xff000004
99 #define MT_STRONLY_ORDER 0
100 #define MT_NORMAL_NC 1
101 #define MT_DEVICE_MEM 4
102 #define MT_NORMAL 7
103
104 /* The phy_addr must be aligned to 4KB */
set_pgtable(u32 * page_table,u32 index,u32 phy_addr)105 static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
106 {
107 u32 value = phy_addr | PMD_TYPE_TABLE;
108
109 page_table[2 * index] = value;
110 page_table[2 * index + 1] = 0;
111 }
112
113 /* The phy_addr must be aligned to 4KB */
set_pgsection(u32 * page_table,u32 index,u64 phy_addr,u32 memory_type)114 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
115 u32 memory_type)
116 {
117 u64 value;
118
119 value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
120 value |= PMD_ATTRINDX(memory_type);
121 page_table[2 * index] = value & 0xFFFFFFFF;
122 page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
123 }
124
125 /*
126 * Start MMU after DDR is available, we create MMU table in DRAM.
127 * The base address of TTLB is gd->arch.tlb_addr. We use two
128 * levels of translation tables here to cover 40-bit address space.
129 *
130 * The TTLBs are located at PHY 2G~4G.
131 *
132 * VA mapping:
133 *
134 * ------- <---- 0GB
135 * | |
136 * | |
137 * |-------| <---- 0x24000000
138 * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
139 * |-------| <---- 0x300000000
140 * | |
141 * |-------| <---- 0x34000000
142 * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
143 * |-------| <---- 0x40000000
144 * | |
145 * |-------| <---- 0x80000000 DDR0 space start
146 * |\\\\\\\|
147 *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
148 * |\\\\\\\|
149 * ------- <---- 4GB DDR0 space end
150 */
mmu_setup(void)151 static void mmu_setup(void)
152 {
153 u32 *level0_table = (u32 *)gd->arch.tlb_addr;
154 u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
155 u64 va_start = 0;
156 u32 reg;
157 int i;
158
159 /* Level 0 Table 2-3 are used to map DDR */
160 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
161 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
162 /* Level 0 Table 1 is used to map device */
163 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
164 /* Level 0 Table 0 is used to map device including PCIe MEM */
165 set_pgtable(level0_table, 0, (u32)level1_table);
166
167 /* Level 1 has 512 entries */
168 for (i = 0; i < 512; i++) {
169 /* Mapping for PCIe 1 */
170 if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR &&
171 va_start < (CFG_SYS_PCIE1_VIRT_ADDR +
172 CFG_SYS_PCIE_MMAP_SIZE))
173 set_pgsection(level1_table, i,
174 CFG_SYS_PCIE1_PHYS_BASE + va_start,
175 MT_DEVICE_MEM);
176 /* Mapping for PCIe 2 */
177 else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR &&
178 va_start < (CFG_SYS_PCIE2_VIRT_ADDR +
179 CFG_SYS_PCIE_MMAP_SIZE))
180 set_pgsection(level1_table, i,
181 CFG_SYS_PCIE2_PHYS_BASE + va_start,
182 MT_DEVICE_MEM);
183 else
184 set_pgsection(level1_table, i,
185 va_start,
186 MT_DEVICE_MEM);
187 va_start += BLOCK_SIZE_L2;
188 }
189
190 asm volatile("dsb sy;isb");
191 asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
192 : : "r" (TTBCR) : "memory");
193 asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
194 : : "r" ((u32)level0_table), "r" (0) : "memory");
195 asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
196 : : "r" (MT_MAIR0) : "memory");
197 asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
198 : : "r" (MT_MAIR1) : "memory");
199
200 /* Set the access control to all-supervisor */
201 asm volatile("mcr p15, 0, %0, c3, c0, 0"
202 : : "r" (~0));
203
204 /* Enable the mmu */
205 reg = get_cr();
206 set_cr(reg | CR_M);
207 }
208
209 /*
210 * This function is called from lib/board.c. It recreates MMU
211 * table in main memory. MMU and i/d-cache are enabled here.
212 */
enable_caches(void)213 void enable_caches(void)
214 {
215 /* Invalidate all TLB */
216 mmu_page_table_flush(gd->arch.tlb_addr,
217 gd->arch.tlb_addr + gd->arch.tlb_size);
218 /* Set up and enable mmu */
219 mmu_setup();
220
221 /* Invalidate & Enable d-cache */
222 invalidate_dcache_all();
223 set_cr(get_cr() | CR_C);
224 }
225 #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
226
get_svr(void)227 uint get_svr(void)
228 {
229 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
230
231 return in_be32(&gur->svr);
232 }
233
234 #if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo(void)235 int print_cpuinfo(void)
236 {
237 char buf1[32], buf2[32];
238 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
239 unsigned int svr, major, minor, ver, i;
240
241 svr = in_be32(&gur->svr);
242 major = SVR_MAJ(svr);
243 minor = SVR_MIN(svr);
244
245 puts("CPU: Freescale LayerScape ");
246
247 ver = SVR_SOC_VER(svr);
248 switch (ver) {
249 case SOC_VER_SLS1020:
250 puts("SLS1020");
251 break;
252 case SOC_VER_LS1020:
253 puts("LS1020");
254 break;
255 case SOC_VER_LS1021:
256 puts("LS1021");
257 break;
258 case SOC_VER_LS1022:
259 puts("LS1022");
260 break;
261 default:
262 puts("Unknown");
263 break;
264 }
265
266 if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
267 puts("E");
268
269 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
270
271 puts("Clock Configuration:");
272
273 printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
274 printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
275 printf("DDR:%-4s MHz (%s MT/s data rate), ",
276 strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
277 puts("\n");
278
279 /* Display the RCW, so that no one gets confused as to what RCW
280 * we're actually using for this boot.
281 */
282 puts("Reset Configuration Word (RCW):");
283 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
284 u32 rcw = in_be32(&gur->rcwsr[i]);
285
286 if ((i % 4) == 0)
287 printf("\n %08x:", i * 4);
288 printf(" %08x", rcw);
289 }
290 puts("\n");
291
292 return 0;
293 }
294 #endif
295
296 #ifdef CONFIG_FSL_ESDHC
cpu_mmc_init(struct bd_info * bis)297 int cpu_mmc_init(struct bd_info *bis)
298 {
299 return fsl_esdhc_mmc_init(bis);
300 }
301 #endif
302
arch_cpu_init(void)303 int arch_cpu_init(void)
304 {
305 void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
306 void *rcpm2_base =
307 (void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
308 struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
309 u32 state;
310
311 icache_enable();
312
313 /*
314 * The RCPM FSM state may not be reset after power-on.
315 * So, reset them.
316 */
317 state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
318 CPMFSMSR_FSM_STATE_MASK;
319 if (state != 0) {
320 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
321 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
322 }
323
324 state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
325 CPMFSMSR_FSM_STATE_MASK;
326 if (state != 0) {
327 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
328 out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
329 }
330
331 /*
332 * After wakeup from deep sleep, Clear EPU registers
333 * as early as possible to prevent from possible issue.
334 * It's also safe to clear at normal boot.
335 */
336 fsl_epu_clean(epu_base);
337
338 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
339
340 return 0;
341 }
342
343 #ifdef CONFIG_ARMV7_NONSEC
344 /* Set the address at which the secondary core starts from.*/
smp_set_core_boot_addr(unsigned long addr,int corenr)345 void smp_set_core_boot_addr(unsigned long addr, int corenr)
346 {
347 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
348
349 out_be32(&gur->scratchrw[0], addr);
350 }
351
352 /* Release the secondary core from holdoff state and kick it */
smp_kick_all_cpus(void)353 void smp_kick_all_cpus(void)
354 {
355 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
356
357 out_be32(&gur->brrl, 0x2);
358
359 /*
360 * LS1 STANDBYWFE is not captured outside the ARM module in the soc.
361 * So add a delay to wait bootrom execute WFE.
362 */
363 udelay(1);
364
365 asm volatile("sev");
366 }
367 #endif
368
reset_cpu(void)369 void reset_cpu(void)
370 {
371 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
372
373 clrbits_be16(&wdog->wcr, WCR_SRS);
374
375 while (1) {
376 /*
377 * Let the watchdog trigger
378 */
379 }
380 }
381
arch_preboot_os(void)382 void arch_preboot_os(void)
383 {
384 unsigned long ctrl;
385
386 /* Disable PL1 Physical Timer */
387 asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
388 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
389 asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
390 }
391
392 #ifdef CONFIG_ARCH_MISC_INIT
arch_misc_init(void)393 int arch_misc_init(void)
394 {
395 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
396 struct udevice *dev;
397 int ret;
398
399 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
400 if (ret)
401 printf("Failed to initialize caam_jr: %d\n", ret);
402 }
403
404 return 0;
405 }
406 #endif
407