Searched refs:cpc (Results 1 – 5 of 5) sorted by relevance
| /arch/arm/mach-sunxi/ |
| A D | clock_sun50i_h6.c | 146 void *const cpc = (void *)SUNXI_CPU_PLL_CFG_BASE; in clock_a523_set_cpu_plls() local
154 writel(val, cpc + CPC_CPUA_CLK_REG); in clock_a523_set_cpu_plls()
155 writel(val, cpc + CPC_CPUB_CLK_REG); in clock_a523_set_cpu_plls()
158 cpc + CPC_DSU_CLK_REG); in clock_a523_set_cpu_plls()
161 clock_set_pll(cpc + CPC_CPUA_PLL_CTRL, n_factor); in clock_a523_set_cpu_plls()
162 clock_set_pll(cpc + CPC_CPUB_PLL_CTRL, n_factor); in clock_a523_set_cpu_plls()
163 clock_set_pll(cpc + CPC_DSU_PLL_CTRL, n_factor); in clock_a523_set_cpu_plls()
166 clrsetbits_le32(cpc + CPC_CPUA_CLK_REG, CPU_CLK_SRC_HOSC, in clock_a523_set_cpu_plls()
168 clrsetbits_le32(cpc + CPC_CPUB_CLK_REG, CPU_CLK_SRC_HOSC, in clock_a523_set_cpu_plls()
170 clrsetbits_le32(cpc + CPC_DSU_CLK_REG, CPU_CLK_SRC_HOSC, in clock_a523_set_cpu_plls()
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| /arch/powerpc/cpu/mpc85xx/ |
| A D | cpu_init.c | 163 for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { in disable_cpc_sram()
164 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { in disable_cpc_sram()
175 out_be32(&cpc->cpccsr0, 0); in disable_cpc_sram()
176 out_be32(&cpc->cpcsrcr0, 0); in disable_cpc_sram()
233 for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { in enable_cpc()
240 cpccfg0 = in_be32(&cpc->cpccfg0); in enable_cpc()
250 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); in enable_cpc()
254 setbits_be32(&cpc->cpchdbcr0, in enable_cpc()
261 in_be32(&cpc->cpccsr0); in enable_cpc()
274 for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { in invalidate_cpc()
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| A D | fdt.c | 166 cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR; in ft_fixup_l3cache() local
167 u32 cfg0 = in_be32(&cpc->cpccfg0); in ft_fixup_l3cache()
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| /arch/powerpc/dts/ |
| A D | t104xsi-pre.dtsi | 54 next-level-cache = <&cpc>;
64 next-level-cache = <&cpc>;
74 next-level-cache = <&cpc>;
84 next-level-cache = <&cpc>;
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| A D | t1040si-post.dtsi | 359 cpc: l3-cache-controller@10000 { label
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