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Searched refs:cpll_pdiv (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init.h51 unsigned cpll_pdiv; member
A Dclock_init_exynos5.c148 .cpll_pdiv = 0x4,
271 .cpll_pdiv = 0x4,
374 .cpll_pdiv = 0x4,
586 writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock); in exynos5250_system_clock_init()
640 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); in exynos5250_system_clock_init()
796 writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock); in exynos5420_system_clock_init()
869 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); in exynos5420_system_clock_init()

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