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/arch/arm/dts/
A Dthunderx-88xx.dtsi24 cpu@000 {
30 cpu@001 {
36 cpu@002 {
42 cpu@003 {
48 cpu@004 {
54 cpu@005 {
60 cpu@006 {
66 cpu@007 {
72 cpu@008 {
78 cpu@009 {
[all …]
A Dsynquacer-sc2a11.dtsi42 CPU0: cpu@0 {
49 CPU1: cpu@1 {
56 CPU2: cpu@100 {
63 CPU3: cpu@101 {
70 CPU4: cpu@200 {
77 CPU5: cpu@201 {
84 CPU6: cpu@300 {
91 CPU7: cpu@301 {
98 CPU8: cpu@400 {
105 CPU9: cpu@401 {
[all …]
A Djuno-r2.dts40 cpu-map {
43 cpu = <&A72_0>;
46 cpu = <&A72_1>;
88 A72_0: cpu@0 {
106 A72_1: cpu@1 {
245 cpu = <&A72_0>;
249 cpu = <&A72_1>;
253 cpu = <&A53_0>;
257 cpu = <&A53_1>;
261 cpu = <&A53_2>;
[all …]
A Dhi6220.dtsi25 cpu-map {
28 cpu = <&cpu0>;
31 cpu = <&cpu1>;
34 cpu = <&cpu2>;
37 cpu = <&cpu3>;
42 cpu = <&cpu4>;
56 cpu0: cpu@0 {
63 cpu1: cpu@1 {
70 cpu2: cpu@2 {
77 cpu3: cpu@3 {
[all …]
A Dmt8183.dtsi26 cpu-map {
29 cpu = <&cpu0>;
32 cpu = <&cpu1>;
35 cpu = <&cpu2>;
38 cpu = <&cpu3>;
58 cpu0: cpu@0 {
66 cpu1: cpu@1 {
74 cpu2: cpu@2 {
82 cpu3: cpu@3 {
90 cpu4: cpu@100 {
[all …]
A Dbcm2837.dtsi43 cpu0: cpu@0 {
44 device_type = "cpu";
48 cpu-release-addr = <0x0 0x000000d8>;
51 cpu1: cpu@1 {
52 device_type = "cpu";
56 cpu-release-addr = <0x0 0x000000e0>;
59 cpu2: cpu@2 {
60 device_type = "cpu";
64 cpu-release-addr = <0x0 0x000000e8>;
67 cpu3: cpu@3 {
[all …]
A Darmada-ap80x-quad.dtsi19 cpu@000 {
22 device_type = "cpu";
27 cpu@001 {
30 device_type = "cpu";
35 cpu@100 {
38 device_type = "cpu";
43 cpu@101 {
46 device_type = "cpu";
A Dfsl-imx8-ca53.dtsi23 CPU_SLEEP: cpu-sleep {
44 A53_0: cpu@0 {
45 device_type = "cpu";
50 cpu-idle-states = <&CPU_SLEEP>;
53 A53_1: cpu@1 {
54 device_type = "cpu";
59 cpu-idle-states = <&CPU_SLEEP>;
62 A53_2: cpu@2 {
63 device_type = "cpu";
71 A53_3: cpu@3 {
[all …]
A Dfsl-imx8-ca35.dtsi15 A35_0: cpu@0 {
16 device_type = "cpu";
24 A35_1: cpu@1 {
25 device_type = "cpu";
33 A35_2: cpu@2 {
34 device_type = "cpu";
42 A35_3: cpu@3 {
43 device_type = "cpu";
A Dnuvoton-npcm845.dtsi15 cpu0: cpu@0 {
16 device_type = "cpu";
24 cpu1: cpu@1 {
25 device_type = "cpu";
33 cpu2: cpu@2 {
34 device_type = "cpu";
42 cpu3: cpu@3 {
43 device_type = "cpu";
A Dbcm2836.dtsi44 v7_cpu0: cpu@0 {
45 device_type = "cpu";
51 v7_cpu1: cpu@1 {
52 device_type = "cpu";
58 v7_cpu2: cpu@2 {
59 device_type = "cpu";
65 v7_cpu3: cpu@3 {
66 device_type = "cpu";
A Dpxa1908.dtsi17 cpu0: cpu@0 {
18 device_type = "cpu";
24 cpu1: cpu@1 {
25 device_type = "cpu";
31 cpu2: cpu@2 {
32 device_type = "cpu";
38 cpu3: cpu@3 {
39 device_type = "cpu";
A Dsun8i-t113s.dtsi17 cpu0: cpu@0 {
19 device_type = "cpu";
22 clock-names = "cpu";
25 cpu1: cpu@1 {
27 device_type = "cpu";
30 clock-names = "cpu";
A Dfvp-base-revc.dts45 cpu0: cpu@0 {
46 device_type = "cpu";
51 cpu1: cpu@100 {
52 device_type = "cpu";
57 cpu2: cpu@200 {
58 device_type = "cpu";
63 cpu3: cpu@300 {
69 cpu4: cpu@10000 {
75 cpu5: cpu@10100 {
81 cpu6: cpu@10200 {
[all …]
/arch/arm/cpu/armv7/sunxi/
A Dpsci.c30 #define SUNXI_CPU_RST(cpu) (0x40 + (cpu) * 0x40 + 0x0) argument
31 #define SUNXI_CPU_STATUS(cpu) (0x40 + (cpu) * 0x40 + 0x8) argument
46 #define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4) argument
143 cpu = 0; in sunxi_cpu_set_power()
180 BIT(cpu)); in sunxi_cpu_set_reset()
183 BIT(cpu)); in sunxi_cpu_set_reset()
218 BIT(cpu)); in sunxi_cpu_invalidate_cache()
227 u32 cpu = cpuid & 0x3; in sunxi_cpu_power_off() local
269 u32 scr, reg, cpu; in psci_fiq_enter() local
287 cpu = (reg >> 10) & 0x7; in psci_fiq_enter()
[all …]
/arch/arm/mach-imx/imx8m/
A Dpsci.c26 #define EN_Cn_WFI_PDN(cpu) BIT(((((cpu) & 1) * 2) + (((cpu) & 2) * 8))) argument
27 #define GPC_PGC_nCTRL(cpu) (0x800 + ((cpu) * 0x40)) argument
30 #define COREn_A53_SW_PUP_REQ(cpu) BIT(cpu) argument
53 psci_state[cpu] = state; in psci_set_state()
60 *cpu = mpidr & MPIDR_AFF0; in psci_cpu_on_validate_mpidr()
65 if (*cpu >= CONFIG_ARMV8_PSCI_NR_CPUS) in psci_cpu_on_validate_mpidr()
133 u32 cpu = 0; in psci_cpu_on_64() local
144 psci_cpu_on_power_on(cpu); in psci_cpu_on_64()
165 return psci_state[cpu]; in psci_affinity_info_64()
192 u32 cpu = psci_get_cpu_id(); in psci_cpu_off() local
[all …]
/arch/arm/cpu/armv7/
A Dpsci-common.c30 void __secure psci_save(int cpu, u32 pc, u32 context_id) in psci_save() argument
32 psci_target_pc[cpu] = pc; in psci_save()
33 psci_context_id[cpu] = context_id; in psci_save()
37 u32 __secure psci_get_target_pc(int cpu) in psci_get_target_pc() argument
39 return psci_target_pc[cpu]; in psci_get_target_pc()
42 u32 __secure psci_get_context_id(int cpu) in psci_get_context_id() argument
44 return psci_context_id[cpu]; in psci_get_context_id()
/arch/powerpc/cpu/mpc8xxx/
A Dcpu.c238 struct cpu_type *cpu = gd->arch.cpu; in cpu_mask() local
245 if (cpu->num_cores == 0) in cpu_mask()
248 return cpu->mask; in cpu_mask()
255 struct cpu_type *cpu = gd->arch.cpu; in cpu_dsp_mask() local
265 return cpu->dsp_mask; in cpu_dsp_mask()
273 struct cpu_type *cpu = gd->arch.cpu; in cpu_num_dspcores() local
291 struct cpu_type *cpu = gd->arch.cpu; in cpu_numcores() local
297 if (cpu->num_cores == 0) in cpu_numcores()
300 return cpu->num_cores; in cpu_numcores()
329 struct cpu_type *cpu = gd->arch.cpu; in fixup_cpu() local
[all …]
/arch/x86/
A DMakefile5 head-y := arch/x86/cpu/start64.o
8 head-y := arch/x86/cpu/start.o
11 head-y := arch/x86/cpu/start.o
14 head-y = arch/x86/cpu/start_from_tpl.o
16 head-y = arch/x86/cpu/start_from_spl.o
23 head-$(CONFIG_$(PHASE_)X86_16BIT_INIT) += arch/x86/cpu/start16.o
24 head-$(CONFIG_$(PHASE_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o
26 libs-y += arch/x86/cpu/
/arch/arm/mach-imx/mx7/
A Dpsci-mx7.c140 psci_state[cpu] = state; in psci_set_state()
182 u32 cpu = psci_get_cpu_id(); in psci_arch_cpu_entry() local
190 u32 cpu = mpidr & MPIDR_AFF0; in psci_cpu_on() local
195 if (cpu >= IMX7D_PSCI_NR_CPUS) in psci_cpu_on()
211 imx_enable_cpu_ca7(cpu, true); in psci_cpu_on()
218 int cpu; in psci_cpu_off() local
220 cpu = psci_get_cpu_id(); in psci_cpu_off()
289 if (cpu >= IMX7D_PSCI_NR_CPUS) in psci_affinity_info()
299 return psci_state[cpu]; in psci_affinity_info()
397 if (cpu == 0) { in imx_gpcv2_set_cpu_power_gate_by_lpm()
[all …]
/arch/x86/cpu/intel_common/
A Dmicrocode.c98 static void microcode_read_cpu(struct microcode_update *cpu) in microcode_read_cpu() argument
107 rdmsr(MSR_IA32_UCODE_REV, low, cpu->update_revision); in microcode_read_cpu()
110 cpu->processor_signature = result.eax; in microcode_read_cpu()
112 cpu->processor_flags = 0; in microcode_read_cpu()
115 cpu->processor_flags = 1 << ((high >> 18) & 7); in microcode_read_cpu()
118 cpu->processor_signature, cpu->processor_flags, in microcode_read_cpu()
119 cpu->update_revision); in microcode_read_cpu()
125 struct microcode_update cpu, update; in microcode_update_intel() local
134 microcode_read_cpu(&cpu); in microcode_update_intel()
162 if (!(update.processor_signature == cpu.processor_signature && in microcode_update_intel()
[all …]
/arch/powerpc/
A DMakefile3 head-y := arch/powerpc/cpu/$(CPU)/start.o
4 head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o
6 libs-y += arch/powerpc/cpu/$(CPU)/
7 libs-y += arch/powerpc/cpu/
/arch/x86/cpu/
A Dqfw_cpu.c22 char *cpu; in qemu_cpu_fixup() local
71 cpu = malloc(8); in qemu_cpu_fixup()
72 if (!cpu) { in qemu_cpu_fixup()
76 sprintf(cpu, "cpu@%d", cpu_num); in qemu_cpu_fixup()
77 ret = device_bind_driver(pdev, "cpu_qemu", cpu, &dev); in qemu_cpu_fixup()
A Dcpu_x86.c58 int node, cpu; in cpu_x86_get_count() local
65 for (cpu = fdt_first_subnode(gd->fdt_blob, node); in cpu_x86_get_count()
66 cpu >= 0; in cpu_x86_get_count()
67 cpu = fdt_next_subnode(gd->fdt_blob, cpu)) { in cpu_x86_get_count()
70 device_type = fdt_getprop(gd->fdt_blob, cpu, in cpu_x86_get_count()
/arch/arm/mach-stm32mp/stm32mp1/
A Dfdt.c113 static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name) in stm32mp13_fdt_fixup() argument
115 switch (cpu) { in stm32mp13_fdt_fixup()
136 switch (cpu) { in stm32mp13_fdt_fixup()
150 static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name) in stm32mp15_fdt_fixup() argument
154 switch (cpu) { in stm32mp15_fdt_fixup()
174 switch (cpu) { in stm32mp15_fdt_fixup()
222 u32 cpu; in ft_system_setup() local
233 cpu = get_cpu_type(); in ft_system_setup()
237 stm32mp13_fdt_fixup(blob, soc, cpu, name); in ft_system_setup()
240 stm32mp15_fdt_fixup(blob, soc, cpu, name); in ft_system_setup()

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