Searched refs:crlapb_base (Results 1 – 8 of 8) sorted by relevance
44 &crlapb_base->boot_pin_ctrl); in ps_mode_reset()48 &crlapb_base->boot_pin_ctrl); in ps_mode_reset()95 &crlapb_base->boot_mode); in spl_boot_device()97 reg = readl(&crlapb_base->boot_mode); in spl_boot_device()
110 tmp = readl(&crlapb_base->rst_lpd_top); in set_r5_reset()127 writel(tmp, &crlapb_base->rst_lpd_top); in set_r5_reset()134 tmp = readl(&crlapb_base->rst_lpd_top); in release_r5_reset()143 writel(tmp, &crlapb_base->rst_lpd_top); in release_r5_reset()150 tmp = readl(&crlapb_base->cpu_r5_ctrl); in enable_clock_r5()152 writel(tmp, &crlapb_base->cpu_r5_ctrl); in enable_clock_r5()194 u32 val = readl(&crlapb_base->rst_lpd_top); in cpu_status()274 tmp = readl(&crlapb_base->rst_lpd_top); in check_tcm_mode()
359 writel(CRL_APB_SOFT_RESET_CTRL_MASK, &crlapb_base->soft_reset); in do_zynqmp_reboot()
70 tmp = readl(&crlapb_base->rst_cpu_r5); in release_r5_reset()78 writel(tmp, &crlapb_base->rst_cpu_r5); in release_r5_reset()85 tmp = readl(&crlapb_base->cpu_r5_ctrl); in enable_clock_r5()87 writel(tmp, &crlapb_base->cpu_r5_ctrl); in enable_clock_r5()
30 #define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR) macro
44 #define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR) macro
44 #define crlapb_base ((struct crlapb_regs *)VERSAL2_CRL_APB_BASEADDR) macro
68 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) macro
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