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Searched refs:csr_wr (Results 1 – 25 of 26) sorted by relevance

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/arch/mips/mach-octeon/
A Dcvmx-helper-rgmii.c86 csr_wr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64); in __cvmx_helper_rgmii_enable()
90 csr_wr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64); in __cvmx_helper_rgmii_enable()
116 csr_wr(CVMX_ASXX_TX_CLK_SETX(port, interface), 24); in __cvmx_helper_rgmii_enable()
226 csr_wr(CVMX_ASXX_RX_PRT_EN(interface), in __cvmx_helper_rgmii_link_set()
234 csr_wr(CVMX_PKO_REG_READ_IDX, queue); in __cvmx_helper_rgmii_link_set()
290 csr_wr(CVMX_GMXX_TXX_CLK(index, interface), 50); in __cvmx_helper_rgmii_link_set()
294 csr_wr(CVMX_GMXX_TXX_CLK(index, interface), 5); in __cvmx_helper_rgmii_link_set()
298 csr_wr(CVMX_GMXX_TXX_CLK(index, interface), 1); in __cvmx_helper_rgmii_link_set()
311 csr_wr(CVMX_ASXX_RX_PRT_EN(interface), in __cvmx_helper_rgmii_link_set()
318 csr_wr(CVMX_PKO_REG_READ_IDX, queue); in __cvmx_helper_rgmii_link_set()
[all …]
A Dcvmx-helper-xaui.c89 csr_wr(CVMX_CIU_QLM2, ciu_qlm.u64); in __cvmx_helper_xaui_probe()
109 csr_wr(CVMX_CIU_QLM2, ciu_qlm.u64); in __cvmx_helper_xaui_probe()
137 csr_wr(CVMX_GMXX_INF_MODE(interface), mode.u64); in __cvmx_helper_xaui_probe()
192 csr_wr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); in __cvmx_helper_xaui_link_init()
193 csr_wr(CVMX_GMXX_TX_INT_EN(interface), 0x0); in __cvmx_helper_xaui_link_init()
194 csr_wr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); in __cvmx_helper_xaui_link_init()
289 csr_wr(CVMX_GMXX_TX_PRTS(interface), 1); in __cvmx_helper_xaui_link_init()
290 csr_wr(CVMX_GMXX_TXX_SLOT(0, interface), 512); in __cvmx_helper_xaui_link_init()
370 csr_wr(CVMX_GMXX_TXX_APPEND(0, interface), in __cvmx_helper_xaui_enable()
442 csr_wr(CVMX_GMXX_TX_INT_EN(interface), 0x0); in __cvmx_helper_xaui_link_get()
[all …]
A Dcvmx-helper-sgmii.c73 csr_wr(CVMX_PCSX_MISCX_CTL_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_one_time()
109 csr_wr(CVMX_PCSX_ANX_ADV_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_one_time()
233 csr_wr(CVMX_PCSX_MISCX_CTL_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_link()
324 csr_wr(CVMX_GMXX_TXX_SLOT(index, interface), 64); in __cvmx_helper_sgmii_hardware_init_link_speed()
353 csr_wr(CVMX_PCSX_MISCX_CTL_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_link_speed()
396 csr_wr(CVMX_CIU_QLM2, ciu_qlm.u64); in __cvmx_helper_sgmii_hardware_init()
416 csr_wr(CVMX_CIU_QLM2, ciu_qlm.u64); in __cvmx_helper_sgmii_hardware_init()
496 csr_wr(CVMX_GMXX_INF_MODE(interface), mode.u64); in __cvmx_helper_sgmii_probe()
532 csr_wr(CVMX_GMXX_PRTX_CFG(index, interface), in __cvmx_helper_sgmii_enable()
541 csr_wr(CVMX_GMXX_BPID_MAPX(index, interface), in __cvmx_helper_sgmii_enable()
[all …]
A Dcvmx-ipd.c94 csr_wr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64); in cvmx_ipd_config()
98 csr_wr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64); in cvmx_ipd_config()
102 csr_wr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); in cvmx_ipd_config()
106 csr_wr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64); in cvmx_ipd_config()
110 csr_wr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64); in cvmx_ipd_config()
114 csr_wr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64); in cvmx_ipd_config()
119 csr_wr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64); in cvmx_ipd_config()
148 csr_wr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); in cvmx_ipd_enable()
A Dcvmx-helper-jtag.c58 csr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64); in cvmx_helper_qlm_jtag_init()
84 csr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64); in cvmx_helper_qlm_jtag_shift()
92 csr_wr(CVMX_CIU_QLM_JTGD, jtgd.u64); in cvmx_helper_qlm_jtag_shift()
136 csr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64); in cvmx_helper_qlm_jtag_update()
143 csr_wr(CVMX_CIU_QLM_JTGD, jtgd.u64); in cvmx_helper_qlm_jtag_update()
162 csr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64); in cvmx_helper_qlm_jtag_capture()
168 csr_wr(CVMX_CIU_QLM_JTGD, jtgd.u64); in cvmx_helper_qlm_jtag_capture()
A Dcvmx-agl.c62 csr_wr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64); in cvmx_agl_enable()
107 csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); in cvmx_agl_link_set()
170 csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); in cvmx_agl_link_set()
190 csr_wr(CVMX_AGL_GMX_TXX_CLK(port), agl_clk.u64); in cvmx_agl_link_set()
196 csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); in cvmx_agl_link_set()
200 csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); in cvmx_agl_link_set()
207 csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64); in cvmx_agl_link_set()
210 csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64); in cvmx_agl_link_set()
A Dcvmx-helper-agl.c92 csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), gmx_prtx_cfg.u64); in __cvmx_helper_agl_probe()
120 csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64); in __cvmx_helper_agl_probe()
128 csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64); in __cvmx_helper_agl_probe()
136 csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64); in __cvmx_helper_agl_probe()
144 csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64); in __cvmx_helper_agl_probe()
177 csr_wr(CVMX_PKO_REG_READ_IDX, read_idx.u64); in __cvmx_helper_agl_enable()
184 csr_wr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); in __cvmx_helper_agl_enable()
A Docteon_qlm.c132 csr_wr(CVMX_CIU_SOFT_PRST, soft_prst.u64); in __set_qlm_pcie_mode_61xx()
153 csr_wr(CVMX_CIU_SOFT_PRST, soft_prst.u64); in __set_qlm_pcie_mode_61xx()
772 csr_wr(CVMX_SATA_UCTL_CTL, uctl_ctl.u64); in __dlm2_sata_uctl_init_cn70xx()
1748 csr_wr(CVMX_PEMX_ON(0), pemx_on.u64); in __dlmx_setup_pcie_cn70xx()
1767 csr_wr(CVMX_PEMX_ON(0), pemx_on.u64); in __dlmx_setup_pcie_cn70xx()
1782 csr_wr(CVMX_PEMX_ON(1), pemx_on.u64); in __dlmx_setup_pcie_cn70xx()
1811 csr_wr(CVMX_PEMX_ON(1), pemx_on.u64); in __dlmx_setup_pcie_cn70xx()
1830 csr_wr(CVMX_PEMX_ON(1), pemx_on.u64); in __dlmx_setup_pcie_cn70xx()
1848 csr_wr(CVMX_PEMX_ON(2), pemx_on.u64); in __dlmx_setup_pcie_cn70xx()
5110 csr_wr(CVMX_GSERX_CFG(qlm), cfg.u64); in octeon_configure_qlm_cn73xx()
[all …]
A Dcvmx-pko.c219 csr_wr(CVMX_PKO_MEM_IPORT_PTRS, config.u64); in __cvmx_pko2_chip_init()
242 csr_wr(CVMX_PKO_MEM_IPORT_PTRS, config.u64); in __cvmx_pko2_chip_init()
309 csr_wr(CVMX_PKO_REG_CMD_BUF, config.u64); in cvmx_pko_hw_init()
318 csr_wr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64); in cvmx_pko_hw_init()
331 csr_wr(CVMX_PKO_REG_MIN_PKT, min_pkt.u64); in cvmx_pko_hw_init()
342 csr_wr(CVMX_PKO_REG_QUEUE_MODE, 3); in cvmx_pko_hw_init()
344 csr_wr(CVMX_PKO_REG_QUEUE_MODE, 2); in cvmx_pko_hw_init()
346 csr_wr(CVMX_PKO_REG_QUEUE_MODE, 1); in cvmx_pko_hw_init()
348 csr_wr(CVMX_PKO_REG_QUEUE_MODE, 0); in cvmx_pko_hw_init()
375 csr_wr(CVMX_PKO_REG_ENGINE_STORAGEX(i), in cvmx_pko_hw_init()
[all …]
A Dcvmx-helper-ilk.c113 csr_wr(CVMX_ILK_TXX_IDX_CAL(interface), tx_idx.u64); in __cvmx_ilk_clear_cal_cn68xx()
130 csr_wr(CVMX_ILK_TXX_MEM_CAL0(interface), tx_cal0.u64); in __cvmx_ilk_clear_cal_cn68xx()
131 csr_wr(CVMX_ILK_TXX_MEM_CAL1(interface), tx_cal1.u64); in __cvmx_ilk_clear_cal_cn68xx()
140 csr_wr(CVMX_ILK_RXX_IDX_CAL(interface), rx_idx.u64); in __cvmx_ilk_clear_cal_cn68xx()
210 csr_wr(CVMX_ILK_TXX_IDX_CAL(interface), tx_idx.u64); in __cvmx_ilk_write_tx_cal_entry_cn68xx()
360 csr_wr(CVMX_ILK_RXX_IDX_CAL(interface), rx_idx.u64); in __cvmx_ilk_write_rx_cal_entry_cn68xx()
813 csr_wr(CVMX_ILK_GBL_INT_EN, 0x1f); in __cvmx_helper_ilk_link_get()
815 csr_wr(CVMX_ILK_TXX_INT_EN(interface), 0x7); in __cvmx_helper_ilk_link_get()
821 csr_wr(CVMX_ILK_RXX_INT_EN(interface), 0x1e2); in __cvmx_helper_ilk_link_get()
835 csr_wr(CVMX_ILK_RX_LNEX_INT_EN(i), in __cvmx_helper_ilk_link_get()
[all …]
A Dcvmx-helper-npi.c109 csr_wr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64); in __cvmx_helper_npi_enable()
118 csr_wr(CVMX_PEXP_SLI_PORTX_PKIND(port), config.u64); in __cvmx_helper_npi_enable()
132 csr_wr(CVMX_PEXP_SLI_TX_PIPE, config.u64); in __cvmx_helper_npi_enable()
A Dcvmx-helper-loop.c98 csr_wr(CVMX_PIP_PRT_CFGX(offset), port_cfg.u64); in __cvmx_helper_loop_enable()
110 csr_wr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); in __cvmx_helper_loop_enable()
163 csr_wr(CVMX_PKO_REG_LOOPBACK_PKIND, lp_pknd.u64); in __cvmx_helper_loop_enable()
164 csr_wr(CVMX_PKO_REG_LOOPBACK_BPID, lp_bpid.u64); in __cvmx_helper_loop_enable()
A Dcvmx-ilk.c292 csr_wr(CVMX_ILK_TXX_CFG1(interface), ilk_txx_cfg1.u64); in cvmx_ilk_start_interface()
293 csr_wr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64); in cvmx_ilk_start_interface()
411 csr_wr(CVMX_ILK_TXX_IDX_PMAP(interface), in cvmx_ilk_tx_set_channel()
413 csr_wr(CVMX_ILK_TXX_MEM_PMAP(interface), in cvmx_ilk_tx_set_channel()
424 csr_wr(CVMX_ILK_TXX_IDX_PMAP(interface), in cvmx_ilk_tx_set_channel()
426 csr_wr(CVMX_ILK_TXX_MEM_PMAP(interface), in cvmx_ilk_tx_set_channel()
478 csr_wr(CVMX_ILK_RXF_IDX_PMAP, ilk_rxf_idx_pmap.u64); in cvmx_ilk_rx_set_pknd()
479 csr_wr(CVMX_ILK_RXF_MEM_PMAP, chpknd->pknd); in cvmx_ilk_rx_set_pknd()
482 csr_wr(CVMX_ILK_RXF_IDX_PMAP, ilk_rxf_idx_pmap.u64); in cvmx_ilk_rx_set_pknd()
483 csr_wr(CVMX_ILK_RXF_MEM_PMAP, chpknd->pknd); in cvmx_ilk_rx_set_pknd()
[all …]
A Dbootoctlinux.c200 csr_wr(CVMX_MIO_BOOT_LOC_CFGX(region_num & 1), val); in octeon_set_moveable_region()
204 csr_wr(CVMX_MIO_BOOT_LOC_ADR, val); in octeon_set_moveable_region()
209 csr_wr(CVMX_MIO_BOOT_LOC_DAT, data[i]); in octeon_set_moveable_region()
551 csr_wr(CVMX_CIU_PP_RST, 0); in do_bootoctlinux()
601 csr_wr(CVMX_CIU3_NMI, in do_bootoctlinux()
606 csr_wr(CVMX_CIU_NMI, in do_bootoctlinux()
A Dcvmx-helper-ipd.c135 csr_wr(CVMX_PIP_SUB_PKIND_FCSX(0), pkind_fcsx.u64); in cvmx_helper_fcs_op()
141 csr_wr(CVMX_PIP_PRT_CFGX(pknd), port_cfg.u64); in cvmx_helper_fcs_op()
181 csr_wr(CVMX_PIP_PRT_CFGBX(pknd), prt_cfgbx.u64); in __cvmx_helper_ipd_port_setup()
A Dcvmx-helper-bgx.c188 csr_wr(CVMX_XCV_RESET, xcv_reset.u64); in __cvmx_helper_bgx_rgmii_speed()
197 csr_wr(CVMX_XCV_RESET, xcv_reset.u64); in __cvmx_helper_bgx_rgmii_speed()
202 csr_wr(CVMX_XCV_CTL, xcv_ctl.u64); in __cvmx_helper_bgx_rgmii_speed()
210 csr_wr(CVMX_XCV_DLL_CTL, dll_ctl.u64); in __cvmx_helper_bgx_rgmii_speed()
215 csr_wr(CVMX_XCV_DLL_CTL, dll_ctl.u64); in __cvmx_helper_bgx_rgmii_speed()
218 csr_wr(CVMX_XCV_RESET, xcv_reset.u64); in __cvmx_helper_bgx_rgmii_speed()
232 csr_wr(CVMX_XCV_RESET, xcv_reset.u64); in __cvmx_helper_bgx_rgmii_speed()
237 csr_wr(CVMX_XCV_RESET, xcv_reset.u64); in __cvmx_helper_bgx_rgmii_speed()
264 csr_wr(CVMX_XCV_RESET, xcv_reset.u64); in __cvmx_helper_bgx_rgmii_speed()
273 csr_wr(CVMX_XCV_RESET, 0); in __cvmx_helper_bgx_rgmii_speed()
[all …]
A Dcvmx-helper-util.c590 csr_wr(CVMX_GMXX_TX_PRTS(xi.interface), gmx_tx_prts.u64); in __cvmx_helper_setup_gmx()
610 csr_wr(CVMX_GMXX_RX_PRTS(xi.interface), gmx_rx_prts.u64); in __cvmx_helper_setup_gmx()
647 csr_wr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64); in __cvmx_helper_setup_gmx()
675 csr_wr(CVMX_GMXX_TXX_THRESH(index, xi.interface), gmx_tx_thresh.u64); in __cvmx_helper_setup_gmx()
693 csr_wr(CVMX_GMXX_TXX_PIPE(index, xi.interface), in __cvmx_helper_setup_gmx()
A Dcvmx-qlm.c1297 csr_wr(CVMX_GSERX_DLMX_MPLL_MULTIPLIER(qlm, 0), mpll_multiplier.u64); in __cvmx_qlm_set_mult()
1680 csr_wr(CVMX_BGXX_CMR_RX_LMACS(2), bgx_cmr_rx_lmacs.u64); in __cvmx_qlm_get_mode_cn73xx()
1681 csr_wr(CVMX_BGXX_CMR_TX_LMACS(2), bgx_cmr_rx_lmacs.u64); in __cvmx_qlm_get_mode_cn73xx()
1923 csr_wr(CVMX_MIO_PTP_CLOCK_CFG, ptp_clock.u64); in cvmx_qlm_measure_clock()
1929 csr_wr(CVMX_MIO_PTP_CLOCK_CFG, ptp_clock.u64); in cvmx_qlm_measure_clock()
1934 csr_wr(CVMX_MIO_PTP_EVT_CNT, -count); in cvmx_qlm_measure_clock()
1937 csr_wr(CVMX_MIO_PTP_EVT_CNT, 1000000000); in cvmx_qlm_measure_clock()
1942 csr_wr(CVMX_MIO_PTP_CLOCK_CFG, ptp_clock.u64); in cvmx_qlm_measure_clock()
1956 csr_wr(CVMX_MIO_PTP_CLOCK_CFG, ptp_clock.u64); in cvmx_qlm_measure_clock()
A Dcpu.c473 csr_wr(CVMX_SATA_UCTL_SHIM_CFG, shim_cfg.u64); in board_ahci_enable()
A Dcvmx-fpa.c506 csr_wr(CVMX_FPA_POOLX_START_ADDR(pool), pool_start_reg.u64); in cvmx_fpa1_fill_pool()
507 csr_wr(CVMX_FPA_POOLX_END_ADDR(pool), pool_end_reg.u64); in cvmx_fpa1_fill_pool()
A Dcvmx-helper.c1478 csr_wr(CVMX_L2C_CFG, l2c_cfg.u64); in cvmx_helper_initialize_packet_io_node()
1622 csr_wr(CVMX_GMXX_TX_OVR_BP(interface), gmxx_tx_ovr_bp.u64); in cvmx_gmx_set_backpressure_override()
1652 csr_wr(CVMX_GMXX_TX_OVR_BP(port), agl_gmx_tx_ovr_bp.u64); in cvmx_agl_set_backpressure_override()
A Dcvmx-pcie.c1255 csr_wr(CVMX_CIU_QLM1, ciu_qlm.u64); in __cvmx_pcie_rc_initialize_gen2()
1263 csr_wr(CVMX_CIU_QLM0, ciu_qlm.u64); in __cvmx_pcie_rc_initialize_gen2()
2338 csr_wr(CVMX_CIU_QLM1, ciu_qlm.u64); in cvmx_pcie_ep_initialize()
2346 csr_wr(CVMX_CIU_QLM0, ciu_qlm.u64); in cvmx_pcie_ep_initialize()
/arch/mips/mach-octeon/include/mach/
A Dcvmx-fpa1.h101 csr_wr(CVMX_FPA_CTL_STATUS, status.u64); in cvmx_fpa1_enable()
117 csr_wr(CVMX_FPA_CTL_STATUS, status.u64); in cvmx_fpa1_disable()
A Dcvmx-pip.h566 csr_wr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64); in cvmx_pip_config_port()
567 csr_wr(CVMX_PIP_PRT_TAGX(ipd_port), port_tag_cfg.u64); in cvmx_pip_config_port()
585 csr_wr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64); in cvmx_pip_config_vlan_qos()
602 csr_wr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64); in cvmx_pip_config_diffserv_qos()
636 csr_wr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64); in cvmx_pip_get_port_stats()
780 csr_wr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); in cvmx_pip_tag_mask_clear()
806 csr_wr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); in cvmx_pip_tag_mask_set()
848 csr_wr(CVMX_PIP_FRM_LEN_CHKX(sel), frm_len.u64); in cvmx_pip_set_frame_check()
857 csr_wr(CVMX_PIP_FRM_LEN_CHKX(0), frm_len.u64); in cvmx_pip_set_frame_check()
921 csr_wr(CVMX_PIP_BSEL_EXT_POSX(bit), bsel_pos.u64); in cvmx_pip_set_bsel_pos()
[all …]
A Dcvmx-regs.h212 static inline void csr_wr(u64 addr, u64 val) in csr_wr() function
479 #define cvmx_write_csr_node(node, addr, val) csr_wr(addr, val)

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