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Searched refs:ctrl (Results 1 – 25 of 132) sorted by relevance

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/arch/arm/mach-omap2/omap5/
A Dhwinit.c98 (*ctrl)->control_emif1_sdram_config_ext); in io_settings_ddr3()
101 (*ctrl)->control_emif2_sdram_config_ext); in io_settings_ddr3()
108 (*ctrl)->control_port_emif1_sdram_config); in io_settings_ddr3()
113 (*ctrl)->control_port_emif2_sdram_config); in io_settings_ddr3()
116 (*ctrl)->control_ddr_control_ext_0); in io_settings_ddr3()
492 value = readl((*ctrl)->control_pbias); in vmmc_pbias_config()
494 writel(value, (*ctrl)->control_pbias); in vmmc_pbias_config()
497 writel(value, (*ctrl)->control_pbias); in vmmc_pbias_config()
501 value = readl((*ctrl)->control_pbias); in vmmc_pbias_config()
503 writel(value, (*ctrl)->control_pbias); in vmmc_pbias_config()
[all …]
A Ddra7xx_iodelay.c23 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ, in isolate_io()
25 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ, in isolate_io()
37 clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK, in isolate_io()
40 readl((*ctrl)->ctrl_core_sma_sw_0); in isolate_io()
184 ret = calibrate_iodelay((*ctrl)->iodelay_config_base); in __recalibrate_iodelay_start()
192 ret = update_delay_mechanism((*ctrl)->iodelay_config_base); in __recalibrate_iodelay_start()
208 if (readl((*ctrl)->ctrl_core_sma_sw_0) & CTRL_ISOLATE_MASK) in __recalibrate_iodelay_end()
212 writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + in __recalibrate_iodelay_end()
294 ret = calibrate_iodelay((*ctrl)->iodelay_config_base); in late_recalibrate_iodelay()
298 ret = update_delay_mechanism((*ctrl)->iodelay_config_base); in late_recalibrate_iodelay()
[all …]
/arch/arm/mach-orion5x/
A Dcpu.c96 writel(0, &winregs[0].ctrl); in orion5x_config_adr_windows()
102 ORION5X_WIN_ENABLE), &winregs[0].ctrl); in orion5x_config_adr_windows()
104 writel(0, &winregs[1].ctrl); in orion5x_config_adr_windows()
110 ORION5X_WIN_ENABLE), &winregs[1].ctrl); in orion5x_config_adr_windows()
112 writel(0, &winregs[2].ctrl); in orion5x_config_adr_windows()
118 writel(0, &winregs[3].ctrl); in orion5x_config_adr_windows()
124 writel(0, &winregs[4].ctrl); in orion5x_config_adr_windows()
130 writel(0, &winregs[5].ctrl); in orion5x_config_adr_windows()
136 writel(0, &winregs[6].ctrl); in orion5x_config_adr_windows()
142 writel(0, &winregs[7].ctrl); in orion5x_config_adr_windows()
[all …]
/arch/arc/lib/
A Dcache.c281 unsigned int ctrl; in __slc_enable() local
284 ctrl &= ~SLC_CTRL_DIS; in __slc_enable()
290 unsigned int ctrl; in __slc_disable() local
293 ctrl |= SLC_CTRL_DIS; in __slc_disable()
377 unsigned int ctrl; in __slc_entire_op() local
387 ctrl |= SLC_CTRL_IM; in __slc_entire_op()
425 unsigned int ctrl; in __slc_rgn_op() local
443 ctrl |= SLC_CTRL_IM; in __slc_rgn_op()
448 ctrl &= ~SLC_CTRL_RGN_OP_INV; in __slc_rgn_op()
689 unsigned int ctrl; in __before_dc_op() local
[all …]
/arch/arm/mach-lpc32xx/
A Ddevices.c16 static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; variable
25 clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id)); in lpc32xx_uart_init()
34 clrsetbits_le32(&ctrl->clkmode, in lpc32xx_uart_init()
96 clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE); in lpc32xx_usb_init()
102 uint32_t ctrl = readl(&clk->i2cclk_ctrl); in lpc32xx_i2c_init() local
104 ctrl |= CLK_I2C1_ENABLE; in lpc32xx_i2c_init()
106 ctrl |= CLK_I2C2_ENABLE; in lpc32xx_i2c_init()
107 writel(ctrl, &clk->i2cclk_ctrl); in lpc32xx_i2c_init()
/arch/arm/mach-kirkwood/
A Dcache.c13 u32 ctrl; in l2_cache_disable() local
15 ctrl = readfr_extra_feature_reg(); in l2_cache_disable()
16 ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN; in l2_cache_disable()
17 writefr_extra_feature_reg(ctrl); in l2_cache_disable()
/arch/arm/mach-imx/imx9/
A Dclock.c54 u32 ctrl; in decode_pll_vco() local
60 ctrl = readl(&reg->ctrl.reg); in decode_pll_vco()
64 if (!(ctrl & PLL_CTRL_POWERUP)) in decode_pll_vco()
92 u32 ctrl = readl(&reg->ctrl.reg); in decode_pll_out() local
95 if (ctrl & PLL_CTRL_CLKMUX_BYPASS) in decode_pll_out()
98 if (!(ctrl & PLL_CTRL_CLKMUX_EN)) in decode_pll_out()
478 u32 ctrl; in get_clk_src_rate() local
483 ctrl = readl(&ana_regs->arm_pll.ctrl.reg); in get_clk_src_rate()
485 ctrl = readl(&ana_regs->audio_pll.ctrl.reg); in get_clk_src_rate()
488 ctrl = readl(&ana_regs->dram_pll.ctrl.reg); in get_clk_src_rate()
[all …]
/arch/mips/mach-ath79/qca953x/
A Dclk.c35 u32 val, ctrl, xtal, pll, div; in get_clocks() local
41 ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG); in get_clocks()
60 div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) in get_clocks()
81 div = ((ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) in get_clocks()
85 div = ((ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) in get_clocks()
87 if (ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) { in get_clocks()
/arch/mips/mach-ath79/ar934x/
A Dclk.c266 u32 ctrl, cpu, cpupll, ddr, ddrpll; in ar934x_update_clock() local
275 ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); in ar934x_update_clock()
280 if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS) in ar934x_update_clock()
282 else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) in ar934x_update_clock()
287 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
289 else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) in ar934x_update_clock()
294 if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS) in ar934x_update_clock()
296 else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) in ar934x_update_clock()
301 cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_update_clock()
303 ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_update_clock()
[all …]
/arch/arm/mach-apple/
A Drtkit_helper.c76 u32 ctrl; in rtkit_helper_probe() local
87 ctrl = readl(priv->asc + REG_CPU_CTRL); in rtkit_helper_probe()
88 writel(ctrl | REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL); in rtkit_helper_probe()
112 u32 ctrl; in rtkit_helper_remove() local
116 ctrl = readl(priv->asc + REG_CPU_CTRL); in rtkit_helper_remove()
117 writel(ctrl & ~REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL); in rtkit_helper_remove()
/arch/arm/mach-omap2/am33xx/
A Dhw_data.c12 struct omap_sys_ctrl_regs const **ctrl = variable
17 *ctrl = &am33xx_ctrl; in hw_data_init()
A Demif4.c50 const struct ddr_data *data, const struct cmd_control *ctrl, in config_ddr() argument
55 config_cmd_ctrl(ctrl, nr); in config_ddr()
/arch/arm/mach-omap2/omap3/
A Dhw_data.c12 struct omap_sys_ctrl_regs const **ctrl = variable
17 *ctrl = &omap3_ctrl; in hw_data_init()
A Dboot.c46 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; in omap_sys_boot_device()
/arch/arm/mach-nexell/include/mach/
A Ddisplay.h218 struct dp_ctrl_info ctrl; member
227 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
233 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
238 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
244 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
254 struct dp_ctrl_info *ctrl);
/arch/arm/mach-socfpga/
A Dtimer.c22 writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl); in timer_init()
/arch/arm/cpu/armv7/ls102xa/
A Dtimer.c61 unsigned long ctrl, freq; in timer_init() local
71 ctrl = ARCH_TIMER_CTRL_ENABLE; in timer_init()
72 asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl)); in timer_init()
A Dcpu.c384 unsigned long ctrl; in arch_preboot_os() local
387 asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl)); in arch_preboot_os()
388 ctrl &= ~ARCH_TIMER_CTRL_ENABLE; in arch_preboot_os()
389 asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl)); in arch_preboot_os()
/arch/arm/cpu/armv7m/
A Dsystick-timer.c37 uint32_t ctrl; member
72 writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, &systick->ctrl); in timer_init()
75 writel(SYSTICK_CTRL_EN, &systick->ctrl); in timer_init()
A Dmpu.c20 writel(0, &V7M_MPU->ctrl); in disable_mpu()
25 writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_PRIVDEFENA, &V7M_MPU->ctrl); in enable_mpu()
/arch/arm/mach-k3/j784s4/
A Dj784s4_init.c270 int ret, ctrl = 0; in k3_mem_init() local
276 ctrl++; in k3_mem_init()
278 while (ctrl < J784S4_MAX_DDR_CONTROLLERS) { in k3_mem_init()
284 panic("DRAM %d init failed: %d\n", ctrl, ret); in k3_mem_init()
285 ctrl++; in k3_mem_init()
287 printf("Initialized %d DRAM controllers\n", ctrl); in k3_mem_init()
/arch/m68k/cpu/mcf532x/
A Dspeed.c200 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
201 clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE); in clock_pll()
233 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
234 setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE); in clock_pll()
/arch/arm/include/asm/arch-lpc32xx/
A Duart.h19 u32 ctrl; /* Control Register */ member
73 u32 ctrl; /* Control Register */ member
/arch/m68k/include/asm/coldfire/
A Dflexcan.h16 u8 ctrl; /* 0x01 Control */ member
22 u16 ctrl; /* 0x00 Control/Status */
66 u32 ctrl; /* 0x04 Control */ member
/arch/arm/mach-omap2/
A Dsysinfo-common.c26 return (readl((*ctrl)->control_status) & DEVICE_TYPE_MASK) >> in get_device_type()

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