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Searched refs:ctrl_ddrio_1 (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-omap2/omap5/
A Dhw_data.c732 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
741 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
752 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
763 .ctrl_ddrio_1 = 0x04A52000,
775 .ctrl_ddrio_1 = 0x04A52000,
787 .ctrl_ddrio_1 = 0x00000000,
A Dhwinit.c67 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); in io_settings_lpddr2()
87 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); in io_settings_ddr3()
/arch/arm/include/asm/arch-omap5/
A Domap.h249 u32 ctrl_ddrio_1; member

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