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Searched refs:ctrl_lpddr2ch (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-omap2/omap5/
A Dhw_data.c730 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
738 .ctrl_lpddr2ch = 0x0,
749 .ctrl_lpddr2ch = 0x0,
760 .ctrl_lpddr2ch = 0x40404040,
772 .ctrl_lpddr2ch = 0x40404040,
784 .ctrl_lpddr2ch = 0x40404040,
A Dhwinit.c64 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); in io_settings_lpddr2()
65 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); in io_settings_lpddr2()
91 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); in io_settings_ddr3()
95 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); in io_settings_ddr3()
/arch/arm/include/asm/arch-omap5/
A Domap.h246 u32 ctrl_lpddr2ch; member

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