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Searched refs:ddr_mode (Results 1 – 7 of 7) sorted by relevance

/arch/arm/mach-exynos/include/mach/
A Dspl.h42 enum ddr_mode mem_type; /* Type of on-board memory */
A Ddmc.h431 enum ddr_mode { enum
/arch/arm/mach-sc5xx/init/
A Ddmcinit.c307 u32 ddr_mode; member
350 if (dmc.ddr_mode == DDR3_MODE) in calibration_legacy()
352 else if (dmc.ddr_mode == DDR2_MODE) in calibration_legacy()
354 else if (dmc.ddr_mode == LPDDR_MODE) in calibration_legacy()
368 if (dmc.ddr_mode == DDR3_MODE || in calibration_legacy()
369 dmc.ddr_mode == DDR2_MODE) { in calibration_legacy()
379 if (dmc.ddr_mode == DDR3_MODE) in calibration_legacy()
382 if (dmc.ddr_mode == LPDDR_MODE) { in calibration_legacy()
909 dmc.ddr_mode = DDR2_MODE; in __dmc_config()
911 dmc.ddr_mode = DDR3_MODE; in __dmc_config()
/arch/arm/mach-exynos/
A Dclock_init.h40 enum ddr_mode mem_type; /* Memory type */
A Ddmc_common.c75 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode) in update_reset_dll()
A Dclock_init_exynos5.c483 static void clock_get_mem_selection(enum ddr_mode *mem_type, in clock_get_mem_selection()
500 enum ddr_mode mem_type; in get_arm_ratios()
524 enum ddr_mode mem_type; in clock_get_mem_timings()
A Dexynos5_setup.h941 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);

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