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Searched refs:ddrdiv (Results 1 – 3 of 3) sorted by relevance

/arch/mips/mach-ath79/ar934x/
A Dclk.c267 u32 cpudiv, ddrdiv, busdiv; in ar934x_update_clock() local
303 ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_update_clock()
309 gd->mem_clk = ddrclk / (ddrdiv + 1); in ar934x_update_clock()
/arch/mips/mach-ath79/ar933x/
A Dlowlevel_init.S25 #define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ argument
27 ((0x3 & (ddrdiv - 1)) << 10) | \
/arch/mips/mach-ath79/qca953x/
A Dlowlevel_init.S20 #define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ argument
22 ((0x3 & (ddrdiv - 1)) << 10) | \

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