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Searched refs:debug (Results 1 – 25 of 402) sorted by relevance

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/arch/x86/cpu/intel_common/
A Dme_status.c139 debug("ME: FW Partition Table : %s\n", in _intel_me_status()
141 debug("ME: Bringup Loader Failure : %s\n", in _intel_me_status()
143 debug("ME: Firmware Init Complete : %s\n", in _intel_me_status()
164 debug("ME: Progress Phase State : "); in _intel_me_status()
173 debug("%s", in _intel_me_status()
176 debug("0x%02x", gmes->current_state); in _intel_me_status()
183 debug("%s", in _intel_me_status()
186 debug("0x%02x", gmes->current_state); in _intel_me_status()
191 debug("Host communication established"); in _intel_me_status()
193 debug("0x%02x", gmes->current_state); in _intel_me_status()
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A Dmrc.c111 debug("memcfg DDR3 clock %d MHz\n", in report_memory_config()
121 debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); in report_memory_config()
122 debug(" enhanced interleave mode %s\n", in report_memory_config()
124 debug(" rank interleave %s\n", in report_memory_config()
126 debug(" DIMMA %d MB width x%d %s rank%s\n", in report_memory_config()
131 debug(" DIMMB %d MB width x%d %s rank%s\n", in report_memory_config()
171 debug("Using SDRAM SPD data for '%s'\n", in mrc_locate_spd()
200 debug("Starting UEFI PEI System Agent\n"); in sdram_initialise()
202 debug("PEI data at %p:\n", pei_data); in sdram_initialise()
209 debug("Calling MRC at %p\n", data); in sdram_initialise()
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/arch/arm/mach-tegra/tegra124/
A Dcpu.c30 debug("%s entry\n", __func__); in enable_cpu_power_rail()
55 debug("%s entry\n", __func__); in enable_cpu_clocks()
83 debug("%s: Done\n", __func__); in enable_cpu_clocks()
91 debug("%s entry\n", __func__); in remove_cpu_resets()
161 debug("%s entry\n", __func__); in tegra124_init_clocks()
181 debug("Setting up PLLX\n"); in tegra124_init_clocks()
188 debug("Enabling clocks\n"); in tegra124_init_clocks()
233 debug("%s exit\n", __func__); in tegra124_init_clocks()
275 debug("%s: C0NC\n", __func__); in unpower_cpus()
279 debug("%s: CE0\n", __func__); in unpower_cpus()
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/arch/arm/mach-imx/
A Dddrmc-vf610-calibration.c100 debug("BITMAP [0x%p]:\n", bmap); in bitmap_print()
102 debug("%d ", test_bit(i, bmap) ? 1 : 0); in bitmap_print()
104 debug("\n"); in bitmap_print()
106 debug("\n"); in bitmap_print()
147 debug("\nRDLVL: ======================\n"); in ddrmc_cal_dqs_to_dq()
148 debug("RDLVL: DQS to DQ (RDLVL)\n"); in ddrmc_cal_dqs_to_dq()
172 debug("RDLVL: PHY_RDLV_RESP:\t 0x%x\n", tmp); //set 0x40 in ddrmc_cal_dqs_to_dq()
183 debug("RDLVL: PHY_RDLVL_EDGE:\t 0x%x\n", in ddrmc_cal_dqs_to_dq()
190 debug("RDLVL: SW_LVL_MODE:\t 0x%x\n", in ddrmc_cal_dqs_to_dq()
205 debug("\nRDLVL: ---> RDLVL_DL_0\n"); in ddrmc_cal_dqs_to_dq()
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/arch/arm/mach-socfpga/
A Dwrap_handoff_soc64.c40 debug("%s: umctl2 handoff data\n", __func__); in check_endianness()
43 debug("%s: PHY handoff data\n", __func__); in check_endianness()
46 debug("%s: PHY engine handoff data\n", __func__); in check_endianness()
50 debug("%s: Unknown endianness!!\n", __func__); in check_endianness()
113 debug("table length = 0x%x\n", table_len); in socfpga_handoff_read()
114 debug("%s: handoff data =\n{\n", __func__); in socfpga_handoff_read()
117 debug(" {\n"); in socfpga_handoff_read()
121 debug(" No.%d Addr 0x%08x: ", i, *table_x32); in socfpga_handoff_read()
136 debug(" No.%d Addr 0x%08x: ", i, in socfpga_handoff_read()
139 debug(" 0x%08x\n", *table_x32); in socfpga_handoff_read()
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/arch/mips/mach-octeon/
A Dcvmx-helper-fdt.c125 debug("%s: Error parsing FDT node %s\n", in cvmx_fdt_parse_vsc7224_channels()
143 debug("%s(%s): Adding %cx channel %d\n", in cvmx_fdt_parse_vsc7224_channels()
173 debug("%s: Out of memory\n", __func__); in cvmx_fdt_parse_vsc7224_channels()
220 debug("%s: Found mac at %s\n", __func__, in cvmx_fdt_parse_vsc7224_channels()
290 debug("%s(%p)\n", __func__, fdt_addr); in __cvmx_fdt_parse_vsc7224()
293 debug("%s: Already parsed\n", __func__); in __cvmx_fdt_parse_vsc7224()
299 debug("%s: Error parsing FDT node %s\n", in __cvmx_fdt_parse_vsc7224()
306 debug("%s: Out of memory!\n", __func__); in __cvmx_fdt_parse_vsc7224()
389 debug("%s: Parsing channels\n", __func__); in __cvmx_fdt_parse_vsc7224()
398 debug("%s(): Error\n", __func__); in __cvmx_fdt_parse_vsc7224()
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A Dcvmx-helper-board.c57 debug("Cannot find I2C device: %d\n", ret); in cvmx_write_vsc7224_reg()
466 debug("iface=%d ", iface); in __pip_eth_node()
475 debug("eth=%d\n", eth); in __pip_eth_node()
1008 debug(" compatible: %s\n", compat); in __cvmx_helper_78xx_parse_phy()
1049 debug(" nexus PHY found\n"); in __cvmx_helper_78xx_parse_phy()
1068 debug(" Found Octeon MDIO\n"); in __cvmx_helper_78xx_parse_phy()
1071 debug(" MDIO address: 0x%llx\n", in __cvmx_helper_78xx_parse_phy()
1098 debug("%s: EXIT 0\n", __func__); in __cvmx_helper_78xx_parse_phy()
1141 debug("No device tree found.\n"); in __get_phy_info_from_dt()
1278 debug("Unknown PHY host mode\n"); in __get_phy_info_from_dt()
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A Dcvmx-range.c35 static const int debug; variable
67 if (debug) in cvmx_range_find_next_available()
91 if (debug) in cvmx_range_find_last_available()
106 if (debug) in cvmx_range_alloc_ordered()
123 if (debug) in cvmx_range_alloc_ordered()
135 if (debug) in cvmx_range_alloc_ordered()
150 if (debug) { in cvmx_range_alloc_ordered()
180 if (debug) in cvmx_range_reserve()
181 debug("%s: %d: %llx\n", in cvmx_range_reserve()
184 if (debug) { in cvmx_range_reserve()
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A Dcvmx-ilk.c254 debug("\n"); in cvmx_ilk_start_interface()
272 debug("\n\n"); in cvmx_ilk_start_interface()
906 debug("ilk rxx idx cal: 0x%16lx\n", in cvmx_ilk_reg_dump_rx()
911 debug("ilk rxx mem cal0: 0x%16lx\n", in cvmx_ilk_reg_dump_rx()
925 debug("ilk rxx cal idx: %d\n", i); in cvmx_ilk_reg_dump_rx()
980 debug("ilk txx idx cal: 0x%16lx\n", in cvmx_ilk_reg_dump_tx()
999 debug("ilk txx cal idx: %d\n", i); in cvmx_ilk_reg_dump_tx()
1034 debug("link flow control sent\n"); in cvmx_ilk_runtime_status()
1059 debug("rx fifo packet drop\n"); in cvmx_ilk_runtime_status()
1086 debug("rx fifo overflow\n"); in cvmx_ilk_runtime_status()
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A Dcvmx-pko3-queue.c90 else if (debug) in cvmx_pko3_get_queue_base()
115 else if (debug) in cvmx_pko3_get_queue_num()
158 if (debug) in __cvmx_pko3_dq_table_setup()
227 if (debug) in __cvmx_pko3_ipd_dq_register()
371 if (debug) in cvmx_pko3_map_channel()
388 if (debug) in cvmx_pko3_map_channel()
634 if (debug) in cvmx_pko_configure_dq()
648 if (debug) in cvmx_pko_configure_dq()
749 if (debug) in cvmx_pko3_pq_config()
852 if (debug) in cvmx_pko3_sq_config_children()
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A Dcvmx-helper-sfp.c83 debug("%s: select GPIO unknown\n", __func__); in cvmx_qsfp_select()
117 debug("Module is not SFP/SFP+/SFP28/QSFP+\n"); in cvmx_sfp_parse_sfp_buffer()
210 debug("%s: RJ45 adapter\n", __func__); in cvmx_sfp_parse_sfp_buffer()
221 debug("RJ45 gigabit module detected\n"); in cvmx_sfp_parse_sfp_buffer()
234 debug("%s: MXC 2X16\n", __func__); in cvmx_sfp_parse_sfp_buffer()
443 debug("%s: RJ45 adapter\n", __func__); in cvmx_sfp_parse_qsfp_buffer()
449 debug("Unknown module type\n"); in cvmx_sfp_parse_qsfp_buffer()
630 debug("Cannot find I2C device: %d\n", err); in cvmx_sfp_read_i2c_eeprom()
713 debug("%s: Error reading SFP %s EEPROM\n", in cvmx_sfp_check_mod_abs()
1010 debug("%s: Error parsing SFP at node %s\n", in cvmx_sfp_parse_device_tree()
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/arch/x86/lib/fsp/
A Dfsp_common.c34 debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); in fsp_init_phase_pci()
37 debug("fail, error code %x\n", status); in fsp_init_phase_pci()
39 debug("OK\n"); in fsp_init_phase_pci()
49 debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); in board_final_init()
52 debug("fail, error code %x\n", status); in board_final_init()
54 debug("OK\n"); in board_final_init()
68 debug("Cannot find RTC: err=%d\n", ret); in fsp_save_s3_stack()
75 debug("Save stack address to CMOS: err=%d\n", ret); in fsp_save_s3_stack()
/arch/arm/mach-uniphier/debug-uart/
A DMakefile4 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o
5 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o
6 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o
7 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += debug-uart-pro5.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += debug-uart-pxs2.o
9 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += debug-uart-ld6b.o
12 obj-y += debug-uart.o
/arch/arm/mach-kirkwood/
A Dmpp.c26 debug("MPP setup: unknown kirkwood variant\n"); in kirkwood_variant()
44 debug( "initial MPP regs:"); in kirkwood_mpp_conf()
47 debug(" %08x", mpp_ctrl[i]); in kirkwood_mpp_conf()
49 debug("\n"); in kirkwood_mpp_conf()
58 debug("kirkwood_mpp_conf: invalid MPP " in kirkwood_mpp_conf()
63 debug("kirkwood_mpp_conf: requested MPP%u config " in kirkwood_mpp_conf()
82 debug(" final MPP regs:"); in kirkwood_mpp_conf()
85 debug(" %08x", mpp_ctrl[i]); in kirkwood_mpp_conf()
87 debug("\n"); in kirkwood_mpp_conf()
/arch/x86/lib/
A Dacpi.c16 debug("Looking on %p for valid checksum\n", rsdp); in acpi_valid_rsdp()
20 debug("acpi rsdp checksum 1 passed\n"); in acpi_valid_rsdp()
25 debug("acpi rsdp checksum 2 passed\n"); in acpi_valid_rsdp()
48 debug("RSDP found at %p\n", rsdp); in acpi_find_fadt()
52 debug("RSDT found at %p ends at %p\n", rsdt, end); in acpi_find_fadt()
64 debug("FADT found at %p\n", fadt); in acpi_find_fadt()
73 debug("Trying to find the wakeup vector...\n"); in acpi_find_wakeup_vector()
78 debug("No FACS found, wake up from S3 not possible.\n"); in acpi_find_wakeup_vector()
82 debug("FACS found at %p\n", facs); in acpi_find_wakeup_vector()
84 debug("OS waking vector is %p\n", wake_vec); in acpi_find_wakeup_vector()
/arch/arm/cpu/arm926ejs/mxs/
A Dspl_power_init.c62 debug("battmonitor:\t 0x%x\n", in mxs_power_regs_dump()
111 debug("SPL: Setting auto-restart bit\n"); in mxs_power_set_auto_restart()
211 debug("SPL: Battery is good\n"); in mxs_is_batt_good()
239 debug("SPL: Battery is good\n"); in mxs_is_batt_good()
247 debug("SPL: Battery Voltage too low\n"); in mxs_is_batt_good()
492 debug("SPL: Enabling 4P2 regulator\n"); in mxs_power_init_4p2_regulator()
511 debug("SPL: Charging 4P2 capacitor\n"); in mxs_power_init_4p2_regulator()
719 debug("Powering Down\n"); in mxs_powerdown()
806 debug("SPL: Resolving 5V conflict\n"); in mxs_handle_5v_conflict()
864 debug("SPL: 5V VDD good\n"); in mxs_5v_boot()
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A Dspl_mem_init.c95 debug("SPL: Using default SDRAM parameters\n"); in mxs_adjust_memory_params()
103 debug("SPL: Setting mx28 board specific SDRAM parameters\n"); in initialize_dram_values()
106 debug("SPL: Applying SDRAM parameters\n"); in initialize_dram_values()
127 debug("SPL: Applying SDRAM parameters\n"); in initialize_dram_values()
154 debug("SPL: Initialising FRAC0\n"); in mxs_mem_init_clock()
180 debug("SPL: FRAC0 Initialised\n"); in mxs_mem_init_clock()
188 debug("SPL: Setting CPU and HBUS clock frequencies\n"); in mxs_mem_setup_cpu_and_hbus()
222 debug("SPL: Configuring VDDA\n"); in mxs_mem_setup_vdda()
255 debug("SPL: Setting mx23 VDDMEM\n"); in mx23_mem_setup_vddmem()
269 debug("SPL: Initialising mx23 SDRAM Controller\n"); in mx23_mem_init()
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/arch/x86/cpu/ivybridge/
A Dsdram.c68 debug("Cannot find RTC: err=%d\n", ret); in read_seed_from_cmos()
84 debug("Failed to read from RTC %s\n", dev->name); in read_seed_from_cmos()
104 debug("%s: invalid seed checksum\n", __func__); in read_seed_from_cmos()
146 debug("Cannot find RTC: err=%d\n", ret); in write_seeds_to_cmos()
293 debug("MEBASE %llx\n", me_base); in sdram_find()
310 debug("IGD decoded, subtracting "); in sdram_find()
314 debug("%uM UMA", uma_size >> 10); in sdram_find()
322 debug(" and %uM GTT\n", uma_size >> 10); in sdram_find()
353 debug("Available memory above 4GB: %lluM\n", in sdram_find()
489 debug("mrc_input %p\n", pei_data->mrc_input); in dram_init()
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/arch/x86/cpu/broadwell/
A Dsdram.c53 debug("dpt %08x tom %08x\n", dpr, tom); in get_top_of_ram()
119 debug("Cannot get ME (err=%d)\n", ret); in dram_init()
127 debug("Cannot get PCH (err=%d)\n", ret); in dram_init()
139 debug("Cannot get Northbridge (err=%d)\n", ret); in dram_init()
145 debug("Cannot locate SPD (err=%d)\n", ret); in dram_init()
153 debug("prepare_mrc_cache failed: %d\n", ret); in dram_init()
155 debug("PEI version %#x\n", pei_data->pei_version); in dram_init()
158 debug("mrc_common_init() failed(err=%d)\n", ret); in dram_init()
161 debug("Memory init done\n"); in dram_init()
165 debug("sdram_find() failed (err=%d)\n", ret); in dram_init()
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A Drefcode.c82 debug("Extracting code from rmodule at %p\n", hdr); in cpu_run_reference_code()
84 debug("Invalid rmodule magic\n"); in cpu_run_reference_code()
88 debug("Link start address must be 0\n"); in cpu_run_reference_code()
92 debug("Entry point must be 0\n"); in cpu_run_reference_code()
105 debug("Copying refcode from %p to %p, size %x\n", src, dest, size); in cpu_run_reference_code()
109 debug("Zeroing BSS at %p, size %x\n", dest + hdr->bss_begin, size); in cpu_run_reference_code()
113 debug("Running reference code at %p\n", func); in cpu_run_reference_code()
119 debug("Reference code returned %d\n", ret); in cpu_run_reference_code()
122 debug("Refereence code completed\n"); in cpu_run_reference_code()
/arch/powerpc/cpu/mpc83xx/
A Dspd_sdram.c234 debug("\n"); in spd_sdram()
236 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]); in spd_sdram()
259 debug("\n"); in spd_sdram()
292 debug("DDR:bar=0x%08x\n", ecm->bar); in spd_sdram()
293 debug("DDR:ar=0x%08x\n", ecm->ar); in spd_sdram()
324 debug("DDR: caslat SPD bit is %d\n", caslat); in spd_sdram()
656 debug(" with ECC\n"); in spd_sdram()
658 debug(" without ECC\n"); in spd_sdram()
832 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); in spd_sdram()
910 debug("ddr init: CPU FP write method\n"); in ddr_enable_ecc()
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/arch/arm/mach-imx/mx6/
A Dddr.c1138 debug("txp=%d\n", txp); in mx6_lpddr2_cfg()
1140 debug("tcl=%d\n", tcl); in mx6_lpddr2_cfg()
1142 debug("twr=%d\n", twr); in mx6_lpddr2_cfg()
1144 debug("twl=%d\n", twl); in mx6_lpddr2_cfg()
1411 debug("txs=%d\n", txs); in mx6_ddr3_cfg()
1412 debug("txp=%d\n", txp); in mx6_ddr3_cfg()
1415 debug("tcl=%d\n", tcl); in mx6_ddr3_cfg()
1417 debug("trp=%d\n", trp); in mx6_ddr3_cfg()
1418 debug("trc=%d\n", trc); in mx6_ddr3_cfg()
1420 debug("twr=%d\n", twr); in mx6_ddr3_cfg()
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/arch/arm/cpu/armv8/
A Dsysinfo.c111 debug("CLIDR_EL1: 0x%llx\n", clidr_el1); in sysinfo_get_cache_info()
191 debug("L%d Cache:\n", level + 1); in sysinfo_get_cache_info()
193 debug("Associativity of cache:%u\n", cinfo->associativity); in sysinfo_get_cache_info()
194 debug("Number of sets in cache:%u\n", num_sets); in sysinfo_get_cache_info()
195 debug("Cache size in KB:%u\n", cinfo->max_size); in sysinfo_get_cache_info()
220 debug("MIDR: 0x%016llx\n", midr.data); in sysinfo_get_processor_info()
221 debug("MPIDR: 0x%016llx\n", mpidr); in sysinfo_get_processor_info()
269 debug("CPU part number: 0x%x\n", midr.fields.partnum); in sysinfo_get_processor_info()
270 debug("CPU revision: 0x%x\n", midr.fields.revision); in sysinfo_get_processor_info()
272 debug("CPU variant: 0x%x\n", midr.fields.variant); in sysinfo_get_processor_info()
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/arch/arm/mach-tegra/tegra20/
A Demc.c129 debug("%s: RAM code required but not supplied\n", __func__); in find_emc_tables()
155 debug("%s: Could not find tables for RAM code %d\n", __func__, in find_emc_tables()
192 debug("%s: No EMC node found in FDT\n", __func__); in decode_emc()
197 debug("%s: No EMC node reg property\n", __func__); in decode_emc()
216 debug("%s: Missing clock-frequency\n", __func__); in decode_emc()
224 debug("%s: No node found for clock frequency %d\n", __func__, in decode_emc()
232 debug("%s: node '%s' array missing / wrong size\n", __func__, in decode_emc()
249 debug("Warning: no valid EMC (%d), memory timings unset\n", in tegra_set_emc()
254 debug("%s: Table found, setting EMC values as follows:\n", __func__); in tegra_set_emc()
259 debug(" %#x: %#x\n", addr, value); in tegra_set_emc()
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/arch/arm/mach-tegra/tegra210/
A Dxusb-padctl.c301 debug(" timeout\n"); in pcie_phy_enable()
304 debug(" done\n"); in pcie_phy_enable()
320 debug(" timeout\n"); in pcie_phy_enable()
323 debug(" done\n"); in pcie_phy_enable()
338 debug(" timeout\n"); in pcie_phy_enable()
341 debug(" done\n"); in pcie_phy_enable()
357 debug(" timeout\n"); in pcie_phy_enable()
360 debug(" done\n"); in pcie_phy_enable()
375 debug(" timeout\n"); in pcie_phy_enable()
378 debug(" done\n"); in pcie_phy_enable()
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