Searched refs:div4 (Results 1 – 5 of 5) sorted by relevance
32 unsigned int div4; member68 unsigned int div4; member
41 u32 div4; /* 60 */ member
132 offset = pllctl_reg(data->pll, div4) + (i - 3); in configure_main_pll()
276 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {284 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
350 div4p5_clk: div4.5 {360 clock-names = "pll0_sysclk3", "div4.5";
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