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Searched refs:div_fsys1 (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init_exynos4.c68 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in system_clock_init()
A Dclock.c411 div = sub_div = readl(&clk->div_fsys1); in exynos5_get_periph_rate()
505 div = readl(&clk->div_fsys1); in exynos542x_get_periph_rate()
809 ratio = readl(&clk->div_fsys1); in exynos4_get_mmc_clk()
810 pre_ratio = readl(&clk->div_fsys1); in exynos4_get_mmc_clk()
851 addr = (unsigned int)&clk->div_fsys1; in exynos4_set_mmc_clk()
884 addr = (unsigned int)&clk->div_fsys1; in exynos5_set_mmc_clk()
908 addr = (unsigned int)&clk->div_fsys1; in exynos5420_set_mmc_clk()
A Dclock_init_exynos5.c941 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in exynos5420_system_clock_init()
998 div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; in emmc_boot_clk_div_set()
1000 writel(div_mmc, (unsigned int) &clk->div_fsys1); in emmc_boot_clk_div_set()
/arch/arm/mach-exynos/include/mach/
A Dclock.h96 unsigned int div_fsys1; member
333 unsigned int div_fsys1; member
724 unsigned int div_fsys1; member
1132 unsigned int div_fsys1; member

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