Searched refs:div_fsys2 (Results 1 – 4 of 4) sorted by relevance
69 writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); in system_clock_init()
416 div = sub_div = readl(&clk->div_fsys2); in exynos5_get_periph_rate()814 ratio = readl(&clk->div_fsys2); in exynos4_get_mmc_clk()815 pre_ratio = readl(&clk->div_fsys2); in exynos4_get_mmc_clk()861 addr = (unsigned int)&clk->div_fsys2; in exynos4_set_mmc_clk()886 addr = (unsigned int)&clk->div_fsys2; in exynos5_set_mmc_clk()
778 writel(val, &clk->div_fsys2); in exynos5250_system_clock_init()942 writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); in exynos5420_system_clock_init()
97 unsigned int div_fsys2; member334 unsigned int div_fsys2; member725 unsigned int div_fsys2; member1133 unsigned int div_fsys2; member
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