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Searched refs:div_lcd0 (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init_exynos4.c75 writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0); in system_clock_init()
A Dclock.c948 ratio = readl(&clk->div_lcd0); in exynos4_get_lcd_clk()
1115 clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1); in exynos4_set_lcd_clk()
1266 clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16); in exynos4_set_mipi_clk()
/arch/arm/mach-exynos/include/mach/
A Dclock.h92 unsigned int div_lcd0; member

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