Home
last modified time | relevance | path

Searched refs:div_peric4 (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-exynos/
A Dclock.c492 sub_div = readl(&clk->div_peric4); in exynos542x_get_periph_rate()
1387 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK, in exynos5_set_i2s_clk_prescaler()
1536 pre_reg = &clk->div_peric4; in exynos5420_set_spi_clk()
1542 pre_reg = &clk->div_peric4; in exynos5420_set_spi_clk()
1548 pre_reg = &clk->div_peric4; in exynos5420_set_spi_clk()
A Dclock_init_exynos5.c955 writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4); in exynos5420_system_clock_init()
/arch/arm/mach-exynos/include/mach/
A Dclock.h731 unsigned int div_peric4; member
1139 unsigned int div_peric4; /* 0x10020568 */ member

Completed in 18 milliseconds