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Searched refs:dma (Results 1 – 25 of 192) sorted by relevance

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/arch/powerpc/dts/
A Delo3-dma-0.dtsi8 dma0: dma@100300 {
11 compatible = "fsl,elo3-dma";
15 dma-channel@0 {
16 compatible = "fsl,eloplus-dma-channel";
20 dma-channel@80 {
25 dma-channel@100 {
30 dma-channel@180 {
35 dma-channel@300 {
40 dma-channel@380 {
45 dma-channel@400 {
[all …]
A Delo3-dma-1.dtsi8 dma1: dma@101300 {
11 compatible = "fsl,elo3-dma";
15 dma-channel@0 {
16 compatible = "fsl,eloplus-dma-channel";
20 dma-channel@80 {
25 dma-channel@100 {
30 dma-channel@180 {
35 dma-channel@300 {
40 dma-channel@380 {
45 dma-channel@400 {
[all …]
A Dkm8321.dtsi64 dma@82a8 {
67 compatible = "fsl,mpc8321-dma", "fsl,elo-dma";
73 dma-channel@0 {
74 compatible = "fsl,mpc8321-dma-channel",
75 "fsl,elo-dma-channel";
80 dma-channel@80 {
82 "fsl,elo-dma-channel";
87 dma-channel@100 {
89 "fsl,elo-dma-channel";
94 dma-channel@180 {
[all …]
A Dpq3-dma-0.dtsi35 dma@21300 {
38 compatible = "fsl,eloplus-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
A Dpq3-dma-1.dtsi35 dma@c300 {
38 compatible = "fsl,eloplus-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
/arch/arm/dts/
A Dbcm2835-common.dtsi11 dma: dma@7e007000 { label
47 "dma-shared-all";
48 #dma-cells = <1>;
132 dmas = <&dma 17>;
133 dma-names = "audio-rx";
195 dmas = <&dma 2>, <&dma 3>;
196 dma-names = "tx", "rx";
200 dmas = <&dma 13>;
201 dma-names = "rx-tx";
205 dmas = <&dma 6>, <&dma 7>;
[all …]
A Dste-dbx5x0.dtsi526 dma: dma-controller@801C0000 { label
532 #dma-cells = <3>;
751 dma-names = "rx", "tx";
767 dma-names = "rx", "tx";
784 dma-names = "rx", "tx";
801 dma-names = "rx", "tx";
818 dma-names = "rx", "tx";
835 dma-names = "rx", "tx";
848 dma-names = "rx", "tx";
1011 dma-names = "tx";
[all …]
A Dr9a06g032.dtsi114 #dma-cells = <6>;
115 dma-requests = <32>;
292 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
297 dma-channels = <8>;
298 dma-requests = <16>;
299 dma-masters = <1>;
300 #dma-cells = <3>;
306 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
311 dma-channels = <8>;
313 dma-masters = <1>;
[all …]
A Dstm32mp157c-odyssey-som.dtsi32 compatible = "shared-dma-pool";
38 compatible = "shared-dma-pool";
44 compatible = "shared-dma-pool";
50 compatible = "shared-dma-pool";
105 /delete-property/dma-names;
284 /delete-property/dma-names;
299 /delete-property/dma-names;
314 /delete-property/dma-names;
329 /delete-property/dma-names;
344 /delete-property/dma-names;
[all …]
A Ds900.dtsi276 dma: dma-controller@e0260000 { label
283 #dma-cells = <1>;
284 dma-channels = <12>;
295 dmas = <&dma 2>;
296 dma-names = "mmc";
306 dmas = <&dma 3>;
307 dma-names = "mmc";
317 dmas = <&dma 4>;
318 dma-names = "mmc";
328 dmas = <&dma 46>;
[all …]
A Dsama7g5.dtsi436 dma-names = "rx";
497 dma-names = "rx";
509 dma-names = "rx";
521 dma-names = "rx";
533 dma-names = "tx";
609 dma-names = "tx";
631 atmel,use-dma-rx;
632 atmel,use-dma-tx;
788 #dma-cells = <1>;
798 #dma-cells = <1>;
[all …]
A Dimx23.dtsi69 #dma-cells = <1>;
70 dma-channels = <8>;
90 dma-names = "rx-tx";
99 dma-names = "rx-tx";
428 #dma-cells = <1>;
429 dma-channels = <16>;
471 dma-names = "rx-tx";
497 dma-names = "rx-tx";
516 dma-names = "tx";
523 dma-names = "rx";
[all …]
A Dsun6i-a31.dtsi272 dma: dma-controller@1c02000 { label
479 dmas = <&dma 13>, <&dma 13>, <&dma 14>;
769 dmas = <&dma 2>, <&dma 2>;
782 dmas = <&dma 3>, <&dma 3>;
795 dmas = <&dma 4>, <&dma 4>;
822 dmas = <&dma 6>, <&dma 6>;
835 dmas = <&dma 7>, <&dma 7>;
848 dmas = <&dma 8>, <&dma 8>;
861 dmas = <&dma 9>, <&dma 9>;
874 dmas = <&dma 10>, <&dma 10>;
[all …]
A Dzynqmp.dtsi581 #dma-cells = <1>;
594 #dma-cells = <1>;
607 #dma-cells = <1>;
620 #dma-cells = <1>;
633 #dma-cells = <1>;
646 #dma-cells = <1>;
659 #dma-cells = <1>;
672 #dma-cells = <1>;
707 * These dma channels, Users should ensure that these dma
717 #dma-cells = <1>;
[all …]
A Dsunxi-h3-h5.dtsi113 dma-ranges;
151 dma: dma-controller@1c02000 { label
596 dmas = <&dma 23>, <&dma 23>;
612 dmas = <&dma 24>, <&dma 24>;
657 dmas = <&dma 3>, <&dma 3>;
670 dmas = <&dma 4>, <&dma 4>;
697 dmas = <&dma 15>, <&dma 15>;
711 dmas = <&dma 6>, <&dma 6>;
724 dmas = <&dma 7>, <&dma 7>;
737 dmas = <&dma 8>, <&dma 8>;
[all …]
A Domap3.dtsi162 dma-names = "tx", "rx";
212 #dma-cells = <1>;
213 dma-channels = <32>;
214 dma-requests = <96>;
215 ti,hwmods = "dma";
290 dma-names = "tx", "rx";
300 dma-names = "tx", "rx";
310 dma-names = "tx", "rx";
320 dma-names = "tx", "rx";
585 dma-names = "rx";
[all …]
/arch/riscv/dts/
A Dsunxi-d1s-t113.dtsi193 dmas = <&dma 4>, <&dma 4>;
208 dmas = <&dma 5>, <&dma 5>;
241 dmas = <&dma 14>, <&dma 14>;
254 dmas = <&dma 15>, <&dma 15>;
267 dmas = <&dma 16>, <&dma 16>;
280 dmas = <&dma 17>, <&dma 17>;
293 dmas = <&dma 18>, <&dma 18>;
306 dmas = <&dma 19>, <&dma 19>;
319 dmas = <&dma 43>, <&dma 43>;
334 dmas = <&dma 44>, <&dma 44>;
[all …]
/arch/mips/dts/
A Dbrcm,bcm6338.dtsi7 #include <dt-bindings/dma/bcm6338-dma.h>
135 iudma: dma-controller@fffe2400 {
140 reg-names = "dma",
141 "dma-channels",
142 "dma-sram";
143 #dma-cells = <1>;
144 dma-channels = <6>;
157 dma-names = "rx",
A Dbrcm,bcm6348.dtsi7 #include <dt-bindings/dma/bcm6348-dma.h>
171 dma-names = "rx",
184 dma-names = "rx",
190 iudma: dma-controller@fffe7000 {
195 reg-names = "dma",
196 "dma-channels",
197 "dma-sram";
198 #dma-cells = <1>;
199 dma-channels = <4>;
A Dbrcm,bcm6358.dtsi7 #include <dt-bindings/dma/bcm6358-dma.h>
203 dma-names = "rx",
217 dma-names = "rx",
223 iudma: dma-controller@fffe5000 {
228 reg-names = "dma",
229 "dma-channels",
230 "dma-sram";
231 #dma-cells = <1>;
232 dma-channels = <8>;
A Dbrcm,bcm6318.dtsi7 #include <dt-bindings/dma/bcm6318-dma.h>
205 dma-names = "rx",
212 iudma: dma-controller@10088000 {
217 reg-names = "dma",
218 "dma-channels",
219 "dma-sram";
220 #dma-cells = <1>;
221 dma-channels = <8>;
A Dbrcm,bcm6328.dtsi7 #include <dt-bindings/dma/bcm6328-dma.h>
208 iudma: dma-controller@1000d800 {
213 reg-names = "dma",
214 "dma-channels",
215 "dma-sram";
216 #dma-cells = <1>;
217 dma-channels = <8>;
230 dma-names = "rx",
A Dbrcm,bcm6368.dtsi7 #include <dt-bindings/dma/bcm6368-dma.h>
215 iudma: dma-controller@10006800 {
220 reg-names = "dma",
221 "dma-channels",
222 "dma-sram";
223 #dma-cells = <1>;
224 dma-channels = <8>;
239 dma-names = "rx",
A Dbrcm,bcm6362.dtsi7 #include <dt-bindings/dma/bcm6362-dma.h>
234 iudma: dma-controller@1000d800 {
239 reg-names = "dma",
240 "dma-channels",
241 "dma-sram";
242 #dma-cells = <1>;
243 dma-channels = <8>;
258 dma-names = "rx",
A Dbrcm,bcm63268.dtsi7 #include <dt-bindings/dma/bcm63268-dma.h>
240 iudma: dma-controller@1000d800 {
245 reg-names = "dma",
246 "dma-channels",
247 "dma-sram";
248 #dma-cells = <1>;
249 dma-channels = <8>;
269 dma-names = "rx",

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