| /arch/arm/mach-sc5xx/init/ |
| A D | dmcinit.c | 327 } dmc; variable
633 writel(dmc.dmc_cfg_value, dmc.reg + REG_DMC_CFG); in dmc_controller_init()
634 writel(dmc.dmc_tr0_value, dmc.reg + REG_DMC_TR0); in dmc_controller_init()
635 writel(dmc.dmc_tr1_value, dmc.reg + REG_DMC_TR1); in dmc_controller_init()
636 writel(dmc.dmc_tr2_value, dmc.reg + REG_DMC_TR2); in dmc_controller_init()
637 writel(dmc.dmc_mr0_value, dmc.reg + REG_DMC_MR); in dmc_controller_init()
638 writel(dmc.dmc_mr1_value, dmc.reg + REG_DMC_EMR1); in dmc_controller_init()
639 writel(dmc.dmc_mr2_value, dmc.reg + REG_DMC_EMR2); in dmc_controller_init()
642 writel(dmc.dmc_mr3_value, dmc.reg + REG_DMC_EMR3); in dmc_controller_init()
643 writel(dmc.dmc_dllctl_value, dmc.reg + REG_DMC_DLLCTL); in dmc_controller_init()
[all …]
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| /arch/arm/mach-exynos/ |
| A D | dmc_init_exynos4.c | 55 &dmc->phycontrol1); in phy_control_reset()
57 &dmc->phycontrol1); in phy_control_reset()
60 &dmc->phycontrol0); in phy_control_reset()
76 &dmc->directcmd); in dmc_config_mrs()
101 phy_control_reset(1, dmc); in dmc_init()
102 phy_control_reset(0, dmc); in dmc_init()
143 dmc_config_mrs(dmc, 0); in dmc_init()
154 dmc_config_mrs(dmc, 1); in dmc_init()
170 struct exynos4_dmc *dmc; in mem_ctrl_init() local
209 dmc_init(dmc); in mem_ctrl_init()
[all …]
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| A D | dmc_init_ddr3.c | 38 struct exynos5_dmc *dmc; in ddr3_mem_ctrl_init() local
74 &dmc->concontrol); in ddr3_mem_ctrl_init()
104 &dmc->concontrol); in ddr3_mem_ctrl_init()
107 writel(mem->iv_size, &dmc->ivcontrol); in ddr3_mem_ctrl_init()
109 writel(mem->memconfig, &dmc->memconfig0); in ddr3_mem_ctrl_init()
116 &dmc->prechconfig); in ddr3_mem_ctrl_init()
121 &dmc->pwrdnconfig); in ddr3_mem_ctrl_init()
132 dmc_config_prech(mem, &dmc->directcmd); in ddr3_mem_ctrl_init()
135 dmc_config_mrs(mem, &dmc->directcmd); in ddr3_mem_ctrl_init()
183 while ((readl(&dmc->phystatus) & in ddr3_mem_ctrl_init()
[all …]
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| /arch/arm/dts/ |
| A D | rk3368-u-boot.dtsi | 6 #include <dt-bindings/memory/rk3368-dmc.h>
10 dmc: dmc@ff610000 { label
11 compatible = "rockchip,rk3368-dmc", "syscon";
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| A D | rk3128-u-boot.dtsi | 6 dmc: dmc@20004000 { label
7 compatible = "rockchip,rk3128-dmc", "syscon";
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| A D | rk3xxx-u-boot.dtsi | 10 dmc: dmc@20020000 { label
12 compatible = "rockchip,rk3188-dmc", "syscon";
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| A D | rk322x-u-boot.dtsi | 24 dmc: dmc@11200000 { label
25 compatible = "rockchip,rk3228-dmc", "syscon";
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| A D | rk3368-px5-evb-u-boot.dtsi | 14 &dmc {
19 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
38 &dmc {
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| A D | rk3288-u-boot.dtsi | 21 dmc: dmc@ff610000 { label
22 compatible = "rockchip,rk3288-dmc", "syscon";
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| A D | rk3308-u-boot.dtsi | 18 dmc: dmc@ff010000 { label
19 compatible = "rockchip,rk3308-dmc";
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| A D | rv1126-u-boot.dtsi | 14 dmc {
15 compatible = "rockchip,rv1126-dmc";
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| A D | rk3066a-mk808-u-boot.dtsi | 15 &dmc {
16 compatible = "rockchip,rk3066-dmc", "syscon";
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| A D | rk356x-u-boot.dtsi | 19 dmc: dmc { label
20 compatible = "rockchip,rk3568-dmc";
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| A D | rk3328-u-boot.dtsi | 19 dmc: dmc { label
20 compatible = "rockchip,rk3328-dmc";
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| A D | px30-u-boot.dtsi | 18 dmc {
20 compatible = "rockchip,px30-dmc", "syscon";
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| A D | rk3576-u-boot.dtsi | 13 dmc {
14 compatible = "rockchip,rk3576-dmc";
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| A D | rk3588s-u-boot.dtsi | 17 dmc {
18 compatible = "rockchip,rk3588-dmc";
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| A D | rk3326-odroid-go2-u-boot.dtsi | 22 dmc {
24 compatible = "rockchip,px30-dmc", "syscon";
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| A D | rk3368-geekbox-u-boot.dtsi | 16 &dmc {
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| A D | rk3368-sheep-u-boot.dtsi | 16 &dmc {
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| A D | rk3528-u-boot.dtsi | 15 dmc {
16 compatible = "rockchip,rk3528-dmc";
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| A D | rk3288-veyron-jerry-u-boot.dtsi | 5 &dmc {
|
| /arch/riscv/dts/ |
| A D | jh7110-u-boot.dtsi | 21 dmc: dmc@15700000 { label
23 compatible = "starfive,jh7110-dmc";
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| A D | fu740-c000-u-boot.dtsi | 74 dmc: dmc@100b0000 { label
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| A D | fu540-c000-u-boot.dtsi | 78 dmc: dmc@100b0000 { label
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