Home
last modified time | relevance | path

Searched refs:domain (Results 1 – 25 of 70) sorted by relevance

123

/arch/arm/include/asm/mach-imx/
A Drdc-sema.h40 #define RDC_PDAP_DW_SHIFT(domain) ((domain) << 1) argument
41 #define RDC_PDAP_DR_SHIFT(domain) (1 + RDC_PDAP_DW_SHIFT(domain)) argument
42 #define RDC_PDAP_DW_MASK(domain) (1 << RDC_PDAP_DW_SHIFT(domain)) argument
43 #define RDC_PDAP_DR_MASK(domain) (1 << RDC_PDAP_DR_SHIFT(domain)) argument
44 #define RDC_PDAP_DRW_MASK(domain) (RDC_PDAP_DW_MASK(domain) | \ argument
58 #define RDC_MRC_DW_SHIFT(domain) (domain) argument
59 #define RDC_MRC_DR_SHIFT(domain) (1 + RDC_MRC_DW_SHIFT(domain)) argument
60 #define RDC_MRC_DW_MASK(domain) (1 << RDC_MRC_DW_SHIFT(domain)) argument
61 #define RDC_MRC_DR_MASK(domain) (1 << RDC_MRC_DR_SHIFT(domain)) argument
62 #define RDC_MRC_DRW_MASK(domain) (RDC_MRC_DW_MASK(domain) | \ argument
[all …]
/arch/arm/include/asm/proc-armv/
A Ddomain.h43 unsigned int domain = current->thread.domain; \
44 domain &= ~domain_val(dom, DOMAIN_MANAGER); \
45 domain |= domain_val(dom, type); \
46 current->thread.domain = domain; \
47 set_domain(current->thread.domain); \
A Dprocessor.h41 unsigned int domain;
44 domain: domain_val(DOMAIN_USER, DOMAIN_CLIENT) | \
/arch/arm/dts/
A Dt8103-pmgr.dtsi13 #power-domain-cells = <0>;
22 #power-domain-cells = <0>;
31 #power-domain-cells = <0>;
40 #power-domain-cells = <0>;
48 #power-domain-cells = <0>;
56 #power-domain-cells = <0>;
64 #power-domain-cells = <0>;
72 #power-domain-cells = <0>;
81 #power-domain-cells = <0>;
90 #power-domain-cells = <0>;
[all …]
A Dfsl-imx8qm.dtsi93 #power-domain-cells = <0>;
99 #power-domain-cells = <0>;
104 #power-domain-cells = <0>;
109 #power-domain-cells = <0>;
114 #power-domain-cells = <0>;
119 #power-domain-cells = <0>;
124 #power-domain-cells = <0>;
129 #power-domain-cells = <0>;
134 #power-domain-cells = <0>;
142 #power-domain-cells = <0>;
[all …]
A Dfsl-imx8dx.dtsi135 #power-domain-cells = <0>;
141 #power-domain-cells = <0>;
146 #power-domain-cells = <0>;
151 #power-domain-cells = <0>;
156 #power-domain-cells = <0>;
161 #power-domain-cells = <0>;
166 #power-domain-cells = <0>;
171 #power-domain-cells = <0>;
184 #power-domain-cells = <0>;
218 #power-domain-cells = <0>;
[all …]
A Dk3-am654-r5-base-board.dts59 * starting System Firmware, so any clock/power-domain
61 * Delete all clock/power-domain properties to avoid
105 * or power-domain operation will fail as we do not
107 * power-domain properties to avoid making calls to
119 * or power-domain operation will fail as we do not
121 * power-domain properties to avoid making calls to
A Dkeystone-k2e-evm-u-boot.dtsi30 psc-domain = <2>;
44 psc-domain = <1>;
A Dk3-am642-r5-evm.dts77 * so we can't do any power-domain/clock operations.
78 * Delete clock/power-domain properties to avoid
88 * starting System Firmware, so any clock/power-domain
90 * Delete all clock/power-domain properties to avoid
A Dk3-am642-r5-sk.dts72 * so we can't do any power-domain/clock operations.
73 * Delete clock/power-domain properties to avoid
83 * starting System Firmware, so any clock/power-domain
85 * Delete all clock/power-domain properties to avoid
A Dkeystone-k2g-evm-u-boot.dtsi42 psc-domain = <25>;
54 psc-domain = <26>;
A Dmt8365.dtsi305 #power-domain-cells = <1>;
312 #power-domain-cells = <1>;
324 #power-domain-cells = <0>;
341 #power-domain-cells = <0>;
348 #power-domain-cells = <0>;
354 #power-domain-cells = <0>;
371 #power-domain-cells = <0>;
382 #power-domain-cells = <0>;
390 #power-domain-cells = <0>;
400 #power-domain-cells = <0>;
[all …]
A Dk3-am642-r5-phycore-som-2gb.dts105 * starting System Firmware, so any clock/power-domain
107 * Delete all clock/power-domain properties to avoid
119 * so we can't do any power-domain/clock operations.
120 * Delete clock/power-domain properties to avoid
A Dimx8mp.dtsi791 #power-domain-cells = <0>;
796 #power-domain-cells = <0>;
801 #power-domain-cells = <0>;
806 #power-domain-cells = <0>;
810 pgc_mlmix: power-domain@4 {
811 #power-domain-cells = <0>;
1955 #power-domain-cells = <1>;
2023 #power-domain-cells = <1>;
2045 #power-domain-cells = <1>;
2186 linux,pci-domain = <0>;
[all …]
A Dimx8mm.dtsi684 #power-domain-cells = <0>;
691 pgc_pcie: power-domain@1 {
692 #power-domain-cells = <0>;
698 pgc_otg1: power-domain@2 {
699 #power-domain-cells = <0>;
703 pgc_otg2: power-domain@3 {
704 #power-domain-cells = <0>;
720 pgc_gpu: power-domain@5 {
1218 #power-domain-cells = <1>;
1361 linux,pci-domain = <0>;
[all …]
A Dimx8mq.dtsi694 pgc_mipi: power-domain@0 {
712 * domain.
714 pgc_pcie: power-domain@1 {
720 pgc_otg1: power-domain@2 {
725 pgc_otg2: power-domain@3 {
730 pgc_ddr1: power-domain@4 {
735 pgc_gpu: power-domain@5 {
744 pgc_vpu: power-domain@6 {
1506 #power-domain-cells = <1>;
1530 linux,pci-domain = <0>;
[all …]
/arch/arm/mach-imx/
A Drdc-sema.c111 u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE; in imx_rdc_setup_peri() local
114 if (domain == 0) in imx_rdc_setup_peri()
117 reg |= domain; in imx_rdc_setup_peri()
119 share_count = (domain & 0x3) in imx_rdc_setup_peri()
120 + ((domain >> 2) & 0x3) in imx_rdc_setup_peri()
121 + ((domain >> 4) & 0x3) in imx_rdc_setup_peri()
122 + ((domain >> 6) & 0x3); in imx_rdc_setup_peri()
158 u32 domain = (p & RDC_DOMAIN_MASK) >> RDC_DOMAIN_SHIFT_BASE; in imx_rdc_setup_ma() local
160 writel((domain & RDC_MDA_DID_MASK), &imx_rdc->mda[master_id]); in imx_rdc_setup_ma()
/arch/arm/mach-imx/imx9/
A Dclock_root.c199 if (oscpll >= OSCPLL_END || domain >= 16) in ccm_clk_src_config_lpm()
206 if (domain > 7) { in ccm_clk_src_config_lpm()
208 lpm &= ~(0x3 << ((domain - 8) * 4)); in ccm_clk_src_config_lpm()
209 lpm |= (lpm_val & 0x3) << ((domain - 8) * 4); in ccm_clk_src_config_lpm()
213 lpm &= ~(0x3 << (domain * 4)); in ccm_clk_src_config_lpm()
214 lpm |= (lpm_val & 0x3) << (domain * 4); in ccm_clk_src_config_lpm()
358 if (lpcg >= CCGR_NUM || domain >= 16) in ccm_lpcg_config_lpm()
365 if (domain > 7) { in ccm_lpcg_config_lpm()
367 lpm &= ~(0x3 << ((domain - 8) * 4)); in ccm_lpcg_config_lpm()
372 lpm &= ~(0x3 << (domain * 4)); in ccm_lpcg_config_lpm()
[all …]
/arch/arm/mach-imx/imx8ulp/upower/
A Dupower_api.c32 (hdr).domain = (u32)pwr_domain; \
178 int upwr_xcp_set_ddr_retention(enum soc_domain domain, u32 enable, const upwr_callb callb) in upwr_xcp_set_ddr_retention() argument
190 txmsg.hdr.domain = (u32)domain; in upwr_xcp_set_ddr_retention()
334 int upwr_init(enum soc_domain domain, struct mu_type *muptr) in upwr_init() argument
347 pwr_domain = domain; in upwr_init()
384 ping_msg.hdr.domain = pwr_domain; in upwr_init()
A Dupower_api.h80 u32 domain :UPWR_PWDOMAIN_BITS; /* power domain */ member
246 int upwr_init(enum soc_domain domain, struct mu_type *muptr);
251 int upwr_xcp_set_ddr_retention(enum soc_domain domain, u32 enable, const upwr_callb callb);
/arch/mips/dts/
A Dbrcm,bcm6318.dtsi9 #include <dt-bindings/power-domain/bcm6318-power-domain.h>
138 compatible = "brcm,bcm6328-power-domain";
140 #power-domain-cells = <1>;
A Dbrcm,bcm6328.dtsi9 #include <dt-bindings/power-domain/bcm6328-power-domain.h>
167 compatible = "brcm,bcm6328-power-domain";
169 #power-domain-cells = <1>;
A Dbrcm,bcm6362.dtsi9 #include <dt-bindings/power-domain/bcm6362-power-domain.h>
193 compatible = "brcm,bcm6328-power-domain";
195 #power-domain-cells = <1>;
/arch/arm/mach-omap2/omap5/
A DKconfig77 domain on DRA7xx & AM57xx SoCs.
91 domain on DRA7xx & AM57xx SoCs.
115 domain on DRA7xx & AM57xx SoCs.
139 domain on DRA7xx & AM57xx SoCs.
/arch/arm/mach-davinci/include/mach/
A Dda850_lowlevel.h29 unsigned char domain, unsigned char state);

Completed in 43 milliseconds

123