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Searched refs:freeze_controller_base (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-socfpga/
A Dfreeze_controller.c38 &freeze_controller_base->vioctrl + channel_id); in sys_mgr_frzctrl_freeze_req()
80 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
88 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
94 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
99 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
153 clrbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
160 setbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
171 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_thaw_req()
176 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_thaw_req()
196 clrbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
[all …]
A Dscan_manager.c33 static const struct socfpga_freeze_controller *freeze_controller_base = variable
155 clrbits_le32(&freeze_controller_base->hioctrl, in scan_mgr_io_scan_chain_prg()

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