| /arch/arm/dts/ |
| A D | am335x-brxre1.dts | 286 ti,no-reset-on-init;
291 ti,no-reset-on-init;
296 ti,no-reset-on-init;
307 ti,no-idle-on-init;
313 ti,no-idle-on-init;
319 ti,no-idle-on-init;
325 ti,no-idle-on-init;
331 ti,no-idle-on-init;
337 ti,no-idle-on-init;
343 ti,no-idle-on-init;
[all …]
|
| A D | am335x-brsmarc1.dts | 331 ti,no-reset-on-init;
336 ti,no-reset-on-init;
341 ti,no-reset-on-init;
352 ti,no-idle-on-init;
358 ti,no-idle-on-init;
364 ti,no-idle-on-init;
370 ti,no-idle-on-init;
376 ti,no-idle-on-init;
382 ti,no-idle-on-init;
388 ti,no-idle-on-init;
[all …]
|
| A D | am335x-brppt1-mmc.dts | 130 ti,no-reset-on-init;
134 ti,no-reset-on-init;
138 ti,no-reset-on-init;
142 ti,no-reset-on-init;
147 ti,no-reset-on-init;
148 ti,no-idle-on-init;
153 ti,no-reset-on-init;
154 ti,no-idle-on-init;
|
| A D | rk3399-gru-u-boot.dtsi | 64 regulator-init-microvolt = <900000>;
68 regulator-init-microvolt = <900000>;
72 regulator-init-microvolt = <900000>;
76 regulator-init-microvolt = <900000>;
|
| A D | bcm283x-u-boot.dtsi | 10 skip-init;
15 skip-init;
|
| A D | meson-g12b-odroid-go-ultra-u-boot.dtsi | 19 regulator-init-microvolt = <2400000>;
23 regulator-init-microvolt = <875000>;
|
| A D | socfpga_arria10-handoff.dtsi | 36 compatible = "altr,socfpga-a10-clk-init";
257 init-val = <H2F_AXI_MASTER>;
263 init-val = <LWH2F_AXI_MASTER>;
269 init-val = <F2H_AXI_SLAVE>;
275 init-val = <F2SDRAM0_AXI_SLAVE>;
281 init-val = <F2SDRAM1_AXI_SLAVE>;
287 init-val = <F2SDRAM2_AXI_SLAVE>;
|
| /arch/arm/mach-sunxi/dram_timings/ |
| A D | a133_lpddr4.c | 76 clrsetbits_le32(&mctl_ctl->init[0], 0xc0000fff, 1008); in mctl_set_timing_params()
79 writel(0x420000, &mctl_ctl->init[1]); in mctl_set_timing_params()
81 writel(0x1f20000, &mctl_ctl->init[1]); in mctl_set_timing_params()
83 clrsetbits_le32(&mctl_ctl->init[2], 0xff0f, 0xd05); in mctl_set_timing_params()
86 writel(0x34 << 16 | 0x1b, &mctl_ctl->init[3]); /* MR1/MR2 */ in mctl_set_timing_params()
87 writel(0x33 << 16, &mctl_ctl->init[4]); /* MR3 */ in mctl_set_timing_params()
88 writel(para->mr11 << 16 | para->mr12, &mctl_ctl->init[6]); in mctl_set_timing_params()
89 writel(para->tpr1 << 16 | para->mr14, &mctl_ctl->init[7]); in mctl_set_timing_params()
|
| A D | a133_ddr4.c | 65 clrsetbits_le32(&mctl_ctl->init[0], 0xc0000fff, 1008); in mctl_set_timing_params()
66 writel(0x1f20000, &mctl_ctl->init[1]); in mctl_set_timing_params()
67 clrsetbits_le32(&mctl_ctl->init[2], 0xff0f, 0xd05); in mctl_set_timing_params()
70 writel(0x840 << 16 | 0x601, &mctl_ctl->init[3]); /* MR0 / MR1 */ in mctl_set_timing_params()
71 writel(0x8 << 16 | 0x0, &mctl_ctl->init[4]); /* MR2 / MR3 */ in mctl_set_timing_params()
72 writel(0x0 << 16 | 0x400, &mctl_ctl->init[6]); /* MR4 / MR5 */ in mctl_set_timing_params()
73 writel(0x826, &mctl_ctl->init[7]); /* MR6 */ in mctl_set_timing_params()
|
| A D | h616_lpddr4_2133.c | 76 clrsetbits_le32(&mctl_ctl->init[0], 0xC0000FFF, 0x3f0); in mctl_set_timing_params()
77 writel(0x01f20000, &mctl_ctl->init[1]); in mctl_set_timing_params()
78 writel(0x00000d05, &mctl_ctl->init[2]); in mctl_set_timing_params()
80 writel(0x0034001b, &mctl_ctl->init[3]); in mctl_set_timing_params()
81 writel(0x00330000, &mctl_ctl->init[4]); in mctl_set_timing_params()
82 writel(0x00040072, &mctl_ctl->init[6]); in mctl_set_timing_params()
83 writel(0x00240009, &mctl_ctl->init[7]); in mctl_set_timing_params()
|
| A D | a523_ddr3.c | 94 clrsetbits_le32(&mctl_ctl->init[0], 0xc0000fff, 0x156); in mctl_set_timing_params()
95 writel(0x01f20000, &mctl_ctl->init[1]); in mctl_set_timing_params()
96 writel(0x00001700, &mctl_ctl->init[2]); in mctl_set_timing_params()
98 writel(0x1f140004, &mctl_ctl->init[3]); in mctl_set_timing_params()
99 writel(0x00200000, &mctl_ctl->init[4]); in mctl_set_timing_params()
100 writel(0, &mctl_ctl->init[6]); /* ? */ in mctl_set_timing_params()
101 writel(0, &mctl_ctl->init[7]); /* ? */ in mctl_set_timing_params()
|
| A D | a523_lpddr4.c | 101 clrsetbits_le32(&mctl_ctl->init[0], 0xC0000FFF, 0x558); in mctl_set_timing_params()
102 writel(0x01f20000, &mctl_ctl->init[1]); in mctl_set_timing_params()
103 writel(0x00001705, &mctl_ctl->init[2]); in mctl_set_timing_params()
105 writel((mr1 << 16) | mr2, &mctl_ctl->init[3]); in mctl_set_timing_params()
106 writel(0x00330000, &mctl_ctl->init[4]); in mctl_set_timing_params()
107 writel(0x00040072, &mctl_ctl->init[6]); in mctl_set_timing_params()
108 writel(0x00260008, &mctl_ctl->init[7]); in mctl_set_timing_params()
|
| A D | h616_lpddr3.c | 78 writel(0x4f0112, &mctl_ctl->init[0]); in mctl_set_timing_params()
79 writel(0x420000, &mctl_ctl->init[1]); in mctl_set_timing_params()
80 writel(0xd05, &mctl_ctl->init[2]); in mctl_set_timing_params()
81 writel(0x83001c, &mctl_ctl->init[3]); in mctl_set_timing_params()
82 writel(0x00010000, &mctl_ctl->init[4]); in mctl_set_timing_params()
|
| A D | h616_ddr3_1333.c | 89 clrbits_le32(&mctl_ctl->init[0], 3 << 30); in mctl_set_timing_params()
90 writel(0x420000, &mctl_ctl->init[1]); in mctl_set_timing_params()
91 writel(5, &mctl_ctl->init[2]); in mctl_set_timing_params()
92 writel(0x1f140004, &mctl_ctl->init[3]); in mctl_set_timing_params()
93 writel(0x00200000, &mctl_ctl->init[4]); in mctl_set_timing_params()
|
| /arch/x86/cpu/quark/ |
| A D | mrc.c | 41 static const struct mem_init init[] = { variable
166 for (i = 0; i < ARRAY_SIZE(init); i++) { in mrc_mem_init()
169 if (mrc_params->boot_mode & init[i].boot_path) { in mrc_mem_init()
170 uint8_t major = init[i].post_code >> 8 & 0xff; in mrc_mem_init()
171 uint8_t minor = init[i].post_code >> 0 & 0xff; in mrc_mem_init()
175 init[i].init_fn(mrc_params); in mrc_mem_init()
|
| /arch/powerpc/cpu/mpc83xx/ |
| A D | u-boot.lds | 63 .text.init : { *(.text.init) }
64 .data.init : { *(.data.init) }
|
| /arch/m68k/cpu/ |
| A D | u-boot.lds | 74 .text.init : { *(.text.init) }
75 .data.init : { *(.data.init) }
|
| /arch/m68k/dts/ |
| A D | mcf54xx.dtsi | 51 rx-init = <16>;
52 tx-init = <17>;
66 rx-init = <30>;
67 tx-init = <31>;
|
| /arch/powerpc/cpu/mpc85xx/ |
| A D | u-boot.lds | 79 .text.init : { *(.text.init) }
80 .data.init : { *(.data.init) }
|
| /arch/x86/lib/fsp1/ |
| A D | fsp_support.c | 86 fsp_init_f init; in fsp_init() local
134 init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init); in fsp_init()
154 : : "m"(params_ptr), "a"(init) in fsp_init()
165 init(¶ms); in fsp_init()
|
| /arch/arm/mach-sunxi/ |
| A D | dram_sun9i.c | 479 &mctl_ctl->init[0]); in mctl_channel_init()
481 &mctl_ctl->init[1]); in mctl_channel_init()
484 &mctl_ctl->init[3]); in mctl_channel_init()
486 &mctl_ctl->init[4]); in mctl_channel_init()
488 &mctl_ctl->init[5]); in mctl_channel_init()
497 &mctl_ctl->init[0]); in mctl_channel_init()
499 &mctl_ctl->init[1]); in mctl_channel_init()
503 &mctl_ctl->init[2]); in mctl_channel_init()
505 &mctl_ctl->init[3]); in mctl_channel_init()
507 &mctl_ctl->init[4]); in mctl_channel_init()
[all …]
|
| /arch/arm/mach-airoha/an7581/ |
| A D | Makefile | 3 obj-y += init.o
|
| /arch/arm/mach-mediatek/mt7622/ |
| A D | Makefile | 3 obj-y += init.o
|
| /arch/arm/mach-mediatek/mt8183/ |
| A D | Makefile | 3 obj-y += init.o
|
| /arch/arm/mach-mediatek/mt8365/ |
| A D | Makefile | 3 obj-y += init.o
|