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Searched refs:invalidate (Results 1 – 8 of 8) sorted by relevance

/arch/arm/mach-mvebu/
A Dlowlevel.S23 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
24 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
25 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
/arch/arm/mach-npcm/npcm7xx/
A Dl2_cache_pl310_init.S48 @Cache maintenance - invalidate 16 ways (0xffff) - base offset 0x77C
50 STR r1, [r0,#0x77C] @ invalidate by way register at offset 0x77C
52 LDR r1, [r0,#0x77C] @ invalidate by way register at offset 0x77C
/arch/arm/cpu/armv7/
A Dstart.S136 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
219 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
220 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
221 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
A Dcache_v7_asm.S58 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
128 mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
A Dpsci.S200 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
/arch/powerpc/cpu/mpc83xx/hid/
A DKconfig62 bool "Flash invalidate instruction cache"
65 bool "Flash invalidate data cache"
143 bool "Flash invalidate instruction cache"
146 bool "Flash invalidate data cache"
/arch/arm/mach-uniphier/arm32/
A Dlowlevel_init.S62 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
/arch/arm/mach-imx/mx6/
A Dsoc.c36 u32 invalidate; member

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