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/arch/mips/mach-octeon/
A Dcvmx-helper-pko3.c170 enum cvmx_pko3_level_e level; in __cvmx_pko3_config_chan_interface() local
227 level = __cvmx_pko3_sq_lvl_next(level); in __cvmx_pko3_config_chan_interface()
254 level = __cvmx_pko3_sq_lvl_next(level); in __cvmx_pko3_config_chan_interface()
280 level = __cvmx_pko3_sq_lvl_next(level); in __cvmx_pko3_config_chan_interface()
384 level = __cvmx_pko3_sq_lvl_next(level); in __cvmx_pko3_config_pfc_interface()
420 level = __cvmx_pko3_sq_lvl_next(level); in __cvmx_pko3_config_pfc_interface()
445 level = __cvmx_pko3_sq_lvl_next(level); in __cvmx_pko3_config_pfc_interface()
561 level = __cvmx_pko3_sq_lvl_next(level); in __cvmx_pko3_config_gen_interface()
590 level = __cvmx_pko3_sq_lvl_next(level); in __cvmx_pko3_config_gen_interface()
693 level = __cvmx_pko3_sq_lvl_next(level); in __cvmx_pko3_config_null_interface()
[all …]
A Dcvmx-pko3-resources.c95 int cvmx_pko3_num_level_queues(enum cvmx_pko3_level_e level) in cvmx_pko3_num_level_queues() argument
101 nq = cvmx_pko_num_queues_78XX[level]; in cvmx_pko3_num_level_queues()
105 nq = cvmx_pko_num_queues_73XX[level]; in cvmx_pko3_num_level_queues()
108 if (nq == 0 || level >= ne) { in cvmx_pko3_num_level_queues()
109 printf("ERROR: %s: queue level %#x invalid\n", __func__, level); in cvmx_pko3_num_level_queues()
192 int cvmx_pko_alloc_queues(int node, int level, int owner, int base_queue, in cvmx_pko_alloc_queues() argument
196 __cvmx_pko_get_queues_resource_tag(node, level); in cvmx_pko_alloc_queues()
197 int max_num_queues = cvmx_pko3_num_level_queues(level); in cvmx_pko_alloc_queues()
/arch/arm/cpu/armv8/
A Dcache_v8.c353 level = 1; in mmu_map_region()
376 level = 1; in add_map()
417 level = 1; in count_ranges()
476 level = 1; in __pagetable_walk()
661 int indent = va_bits < 39 ? level - 1 : level; in pagetable_print_entry()
949 int level; in mmu_set_region_dcache_behaviour() local
952 for (level = 1; level < 4; level++) { in mmu_set_region_dcache_behaviour()
977 int level; in mmu_change_region_attr_nobreak() local
987 for (level = 1; level < 4; level++) { in mmu_change_region_attr_nobreak()
1010 int level; in mmu_change_region_attr() local
[all …]
A Dsysinfo.c99 int sysinfo_get_cache_info(u8 level, struct cache_info *cinfo) in sysinfo_get_cache_info() argument
113 cache_type = (clidr_el1 >> (3 * level)) & 0x7; in sysinfo_get_cache_info()
136 csselr_el1 = (level << 1); in sysinfo_get_cache_info()
141 debug("CCSIDR_EL1 (Level %d): 0x%llx\n", level + 1, creg.data); in sysinfo_get_cache_info()
191 debug("L%d Cache:\n", level + 1); in sysinfo_get_cache_info()
/arch/powerpc/dts/
A Dt104xsi-pre.dtsi51 next-level-cache = <&L2_1>;
54 next-level-cache = <&cpc>;
61 next-level-cache = <&L2_2>;
64 next-level-cache = <&cpc>;
71 next-level-cache = <&L2_3>;
74 next-level-cache = <&cpc>;
81 next-level-cache = <&L2_4>;
84 next-level-cache = <&cpc>;
A Dp2020.dtsi25 next-level-cache = <&L2>;
30 next-level-cache = <&L2>;
/arch/mips/mach-octeon/include/mach/
A Dcvmx-pko3-resources.h19 int cvmx_pko_alloc_queues(int node, int level, int owner, int base_queue,
30 int cvmx_pko_free_queues(int node, int level, int owner);
34 int cvmx_pko3_num_level_queues(enum cvmx_pko3_level_e level);
/arch/arm/cpu/armv7/
A Dcache_v7_asm.S32 mov r10, #0 @ start clean at cache level 0
34 add r2, r10, r10, lsr #1 @ work out 3x current cache level
37 cmp r1, #2 @ see what cache we have at this level
39 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
68 mov r10, #0 @ swith back to cache level 0
69 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
102 mov r10, #0 @ start clean at cache level 0
104 add r2, r10, r10, lsr #1 @ work out 3x current cache level
107 cmp r1, #2 @ see what cache we have at this level
109 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
[all …]
/arch/arm/dts/
A Dfsl-imx8-ca35.dtsi20 next-level-cache = <&A35_L2>;
29 next-level-cache = <&A35_L2>;
38 next-level-cache = <&A35_L2>;
47 next-level-cache = <&A35_L2>;
A Dnuvoton-npcm845.dtsi20 next-level-cache = <&l2>;
29 next-level-cache = <&l2>;
38 next-level-cache = <&l2>;
47 next-level-cache = <&l2>;
A Dvf610.dtsi8 next-level-cache = <&L2>;
16 cache-level = <2>;
A Dfsl-imx8-ca53.dtsi49 next-level-cache = <&A53_L2>;
58 next-level-cache = <&A53_L2>;
67 next-level-cache = <&A53_L2>;
76 next-level-cache = <&A53_L2>;
A Dcorstone1000-fvp.dts59 next-level-cache = <&L2_0>;
66 next-level-cache = <&L2_0>;
73 next-level-cache = <&L2_0>;
A Dsun50i-a64-pinephone-1.1.dts18 * being off is around 20%. Duty cycle for the lowest brightness level
29 default-brightness-level = <400>;
A Djuno-r2.dts99 next-level-cache = <&A72_L2>;
117 next-level-cache = <&A72_L2>;
135 next-level-cache = <&A53_L2>;
153 next-level-cache = <&A53_L2>;
171 next-level-cache = <&A53_L2>;
189 next-level-cache = <&A53_L2>;
A Dnuvoton-npcm750.dtsi24 next-level-cache = <&l2>;
33 next-level-cache = <&l2>;
A Dsun50i-a64-pinephone-1.2.dts23 * is around 10%. Duty cycle for the lowest brightness level also varries
35 default-brightness-level = <500>;
A Dfsl-imx8qxp.dtsi28 next-level-cache = <&A35_L2>;
36 next-level-cache = <&A35_L2>;
A Dsynquacer-sc2a11-caches.dtsi24 next-level-cache = <&L3>; \
42 cache-level = <3>;
/arch/powerpc/dts/fsl/
A Dp2020si-pre.dtsi25 next-level-cache = <&L2>;
30 next-level-cache = <&L2>;
/arch/arm/
A DKconfig.debug4 bool "Low-level debugging functions"
12 prompt "Low-level debugging port"
16 bool "Low-level debugging via 8250 UART"
/arch/riscv/dts/
A Dqilai-voyager.dts43 next-level-cache = <&L2>;
66 next-level-cache = <&L2>;
89 next-level-cache = <&L2>;
112 next-level-cache = <&L2>;
124 cache-level = <0x2>;
A Dk1.dtsi82 next-level-cache = <&cluster0_l2_cache>;
112 next-level-cache = <&cluster0_l2_cache>;
142 next-level-cache = <&cluster0_l2_cache>;
172 next-level-cache = <&cluster0_l2_cache>;
202 next-level-cache = <&cluster1_l2_cache>;
232 next-level-cache = <&cluster1_l2_cache>;
262 next-level-cache = <&cluster1_l2_cache>;
292 next-level-cache = <&cluster1_l2_cache>;
305 cache-level = <2>;
314 cache-level = <2>;
A Dae350_32.dts42 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
84 next-level-cache = <&L2>;
105 next-level-cache = <&L2>;
116 cache-level = <2>;
/arch/arm/cpu/armv7/ls102xa/
A Dpsci.S96 @ Affinity level 2 - Cluster: only one cluster in LS1021xa.
100 @ Affinity level 1 - Processors: should be in 0xf00 format.
105 @ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
209 @ Verify Affinity level

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