Searched refs:level0_table (Results 1 – 1 of 1) sorted by relevance
| /arch/arm/cpu/armv7/ls102xa/ |
| A D | cpu.c | 153 u32 *level0_table = (u32 *)gd->arch.tlb_addr; in mmu_setup() local
160 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
161 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
163 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
165 set_pgtable(level0_table, 0, (u32)level1_table); in mmu_setup()
194 : : "r" ((u32)level0_table), "r" (0) : "memory"); in mmu_setup()
|
Completed in 4 milliseconds