Home
last modified time | relevance | path

Searched refs:m2 (Results 1 – 25 of 27) sorted by relevance

12

/arch/arm/dts/
A Dsun50i-h5-bananapi-m2-plus.dts6 #include <sunxi-bananapi-m2-plus.dtsi>
10 compatible = "sinovoip,bpi-m2-plus", "allwinner,sun50i-h5";
A Dsun8i-h3-bananapi-m2-plus-v1.2.dts8 #include "sunxi-bananapi-m2-plus-v1.2.dtsi"
12 compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun8i-h3";
A Dsun50i-h5-bananapi-m2-plus-v1.2.dts7 #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
11 compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5";
A Dk3-am65-iot2050-boot-image.dtsi234 "ti/k3-am6548-iot2050-advanced-m2",
245 filename = "ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtbo";
259 filename = "ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtbo";
A Dsunxi-bananapi-m2-plus-v1.2.dtsi6 #include "sunxi-bananapi-m2-plus.dtsi"
A Dsun8i-h3-bananapi-m2-plus.dts45 #include "sunxi-bananapi-m2-plus.dtsi"
49 compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
A Dam33xx-clocks.dtsi210 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
226 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
235 dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
250 dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
267 dpll_per_m2_ck: clock-dpll-per-m2@4ac {
276 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
284 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
A Dsun8i-h2-plus-bananapi-m2-zero.dts5 * Based on sun8i-h3-bananapi-m2-plus.dts, which is:
18 compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus";
44 label = "bananapi-m2-zero:red:pwr";
A Dsun6i-a31s-sinovoip-bpi-m2.dts49 compatible = "sinovoip,bpi-m2", "allwinner,sun6i-a31s";
63 label = "bpi-m2:blue:usr";
68 label = "bpi-m2:green:usr";
73 label = "bpi-m2:red:usr";
A Ddra7xx-clocks.dtsi178 video1_m2_clkin_ck: clock-video1-m2-clkin {
190 video2_m2_clkin_ck: clock-video2-m2-clkin {
229 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
298 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 {
342 dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 {
380 dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 {
418 dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 {
465 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 {
565 dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 {
1329 apll_pcie_m2_ck: clock-apll-pcie-m2 {
[all …]
A Dsun8i-r40-feta40i.dtsi3 // Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
A Dsun8i-r40-oka40i-c.dts3 // Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
A DMakefile556 sun6i-a31s-sinovoip-bpi-m2.dtb \
620 sun8i-h2-plus-bananapi-m2-zero.dtb \
624 sun8i-h3-bananapi-m2-plus.dtb \
625 sun8i-h3-bananapi-m2-plus-v1.2.dtb \
647 sun8i-r40-bananapi-m2-ultra.dtb \
650 sun8i-v40-bananapi-m2-berry.dtb
654 sun50i-h5-bananapi-m2-plus.dtb \
A Dsunxi-bananapi-m2-plus.dtsi74 label = "bananapi-m2-plus:red:pwr";
A Dsun8i-v40-bananapi-m2-berry.dts51 compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40";
A Dsun8i-r40-bananapi-m2-ultra.dts52 compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
/arch/arm/include/asm/arch-omap3/
A Dclock.h35 unsigned int m2; member
42 unsigned int m2; member
/arch/arm/mach-omap2/omap3/
A Dclock.c153 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
207 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
266 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); in dpll4_init_34xx()
296 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); in dpll5_init_34xx()
320 0x0000001F, ptr->m2); in mpu_init_34xx()
351 0x0000001F, ptr->m2); in iva_init_34xx()
403 0xF8000000, ptr->m2 << 27); in dpll3_init_36xx()
457 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); in dpll3_init_36xx()
508 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); in dpll4_init_36xx()
536 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); in dpll5_init_36xx()
[all …]
/arch/xtensa/include/asm/arch-de212/
A Dtie.h74 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
/arch/xtensa/include/asm/arch-dc232b/
A Dtie.h96 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
/arch/xtensa/include/asm/arch-dc233c/
A Dtie.h97 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
/arch/arm/mach-omap2/am33xx/
A Dclock.c23 if (params->m2 >= 0) in setup_post_dividers()
24 writel(params->m2, dpll_regs->cm_div_m2_dpll); in setup_post_dividers()
A DKconfig182 the Computing-Module m2 from bytes at work AG.
/arch/arm/include/asm/arch-am33xx/
A Dclock.h92 s8 m2; member
/arch/arm/mach-omap2/
A Dclocks-common.c80 if (params->m2 >= 0) in setup_post_dividers()
81 writel(params->m2, &dpll_regs->cm_div_m2_dpll); in setup_post_dividers()
299 ddr_clk = ddr_clk / divider / core_dpll_params->m2; in omap_ddr_clk()
754 freq_config1 |= (core_dpll_params->m2 << in freq_update_core()

Completed in 38 milliseconds

12