Searched refs:m5 (Results 1 – 7 of 7) sorted by relevance
45 unsigned int m5; member
13 compatible = "mele,m5", "allwinner,sun7i-a20";
185 dpll_core_m5_ck: clock-dpll-core-m5@484 {
574 sun7i-a20-m5.dtb \
29 if (params->m5 >= 0) in setup_post_dividers()30 writel(params->m5, dpll_regs->cm_div_m5_dpll); in setup_post_dividers()
95 s8 m5; member
499 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5); in dpll4_init_36xx()
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